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https://github.com/livingcomputermuseum/UniBone.git
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6f1b476716
Tweaked MSYN timeout value from 350ns to 400ns to compensate for timing changes with latest PRU code -- MSCP works reliably on PDP-11/84 again.
85 lines
3.0 KiB
C
85 lines
3.0 KiB
C
/* tuning.h: Constants to adapt UNIBUS functions
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Copyright (c) 2019, Joerg Hoppe
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j_hoppe@t-online.de, www.retrocmp.com
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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7-jun-2019 JH entered beta phase
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*/
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#define TUNING_PCB_LEGACY_SECURE
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//#define TUNING_PCB_2018_12_OPTIMIZED
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//#define TUNING_PCB_TEST
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/*** Wait cycles for buslatch access. Depends on PCB, used chips and alofirth ***/
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// A BBB with optimized terminators can reach 8
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// BBG can reach *ALMOST* 9
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// #define BUSLATCHES_GETBYTE_DELAY 10 // Standard
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#if defined(TUNING_PCB_TEST)
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// experimental to test error rates
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#define BUSLATCHES_GETBYTE_DELAY 10
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#define BUSLATCHES_SETBITS_DELAY 4
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#define BUSLATCHES_SETBYTE_DELAY 6
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#elif defined(TUNING_PCB_LEGACY_SECURE)
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/* Secure setting for PCBs <= 2018-12, delivered before June 2019.
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Necessary for longtime ZKMA on critical PCBs.
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BeagleBone: BBB (no BBG)
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U2 (REGSEL): 74AC138
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RN8,9 (DATIN) : 47
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RN10 <1:6>(REGADR): 33
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RN10 <7:8>(REGWRITE): 33
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R6,R7 (REGWRITE TERM): none
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RN6,RN7 (DATOUT inline): 22
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RN4,RN5 [[/DATOUT]] end) -> 1K/-
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*/
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#define BUSLATCHES_GETBYTE_DELAY 11
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#define BUSLATCHES_SETBITS_DELAY 5
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#define BUSLATCHES_SETBYTE_DELAY 7
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#elif defined(TUNING_PCB_2018_12_OPTIMIZED)
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/* Setting for PCB v2018_12 with optimized timing (ticket 21, June 2019)
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BeagleBone: BBB (no BBG)
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U2 (REGSEL): 74AC138 -> 74AHC138
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RN8,9 (DATIN) : 47 -> 68 Ohm
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RN10 <1:6>(REGADR): 33->0 Ohm
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RN10 <7:8>(REGWRITE): 33->0 Ohm
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R6,R7 (REGWRITE TERM): none
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RN6,RN7 (DATOUT inline): 22 -> 27
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RN4,RN5 [[/DATOUT]] end) -> 180/-
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*/
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#define BUSLATCHES_GETBYTE_DELAY 9
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#define BUSLATCHES_SETBITS_DELAY 4
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#define BUSLATCHES_SETBYTE_DELAY 6
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//#define BUSLATCHES_GETBYTE_DELAY 8
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//#define BUSLATCHES_SETBITS_DELAY 3
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//#define BUSLATCHES_SETBYTE_DELAY 5
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#endif
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// UNIBUS timing: Wait to stabilize DATA before MSYN asserted
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// per DEC spec
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// #define UNIBUS_DMA_MASTER_PRE_MSYN_NS 150
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// Josh Dersch on 11/84, also for VAX 11/750
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// Addtional delay on PDP11s with private memory interconnect (PMI)
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// and UNIBUS/PMI translation?
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// Experiments with "250" made still occasional errors.
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#define UNIBUS_DMA_MASTER_PRE_MSYN_NS 400
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