diff --git a/verif/Makefile b/verif/Makefile
index 757f748..ba9c506 100644
--- a/verif/Makefile
+++ b/verif/Makefile
@@ -23,6 +23,8 @@ all: regress
 
 #cver +showpc +cycles=5000 +test=tss8_init.mem +pc=24200 +cycles=2000000 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v
 
+#cver +showpc +cycles=100000 +test=tss8_init.mem +pc=24200 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v > xx
+
 define runone_verilog_regression
 	cver $(CVER_FLAGS) $(1) >$(2);
 	@if grep -q ERROR $(2); then exit 1; fi;
diff --git a/verif/fake_uart.v b/verif/fake_uart.v
index 0e68e21..7d6c1e1 100644
--- a/verif/fake_uart.v
+++ b/verif/fake_uart.v
@@ -1,4 +1,9 @@
 //
+// fake model of uart used for sim
+//
+
+//`define debug_fake_tx 1
+`define debug_fake_rx 1
 
 module fake_uart(clk, reset, 
 		 tx_clk, tx_req, tx_ack, tx_data, tx_empty,
@@ -53,7 +58,9 @@ module fake_uart(clk, reset,
 	     t_delay = t_delay - 1;
 	     if (t_delay == 0)
 	       t_done = 1;
-	     if (0) $display("t_state %d t_delay %d", t_state, t_delay);
+`ifdef debug_fake_tx
+	     $display("t_state %d t_delay %d", t_state, t_delay);
+`endif
 	  end
 	if (t_state == 0)
 	  t_done = 0;
@@ -77,11 +84,12 @@ module fake_uart(clk, reset,
    initial
      begin
 	r_index= 0;
-	r_count = 6;
+	r_count = 23;
      end
 
-   reg [7:0] rdata[5:0];
+   reg [7:0] rdata[23:0];
 
+   /* "START\r01:01:85\r10:10\r\r\r" */
    initial
      begin
 	rdata[0] = "S";
@@ -90,6 +98,23 @@ module fake_uart(clk, reset,
 	rdata[3] = "R";
 	rdata[4] = "T";
 	rdata[5] = "\015";
+	rdata[6] = "0";
+	rdata[7] = "1";
+	rdata[8] = ":";
+	rdata[9] = "0";
+	rdata[10] = "1";
+	rdata[11] = ":";
+	rdata[12] = "8";
+	rdata[13] = "5";
+	rdata[14] = "\015";
+	rdata[15] = "1";
+	rdata[16] = "0";
+	rdata[17] = ":";
+	rdata[18] = "1";
+	rdata[19] = "0";
+	rdata[20] = "\015";
+	rdata[21] = "\015";
+	rdata[22] = "\015";
 
 	rx_data = 0;
      end
@@ -99,7 +124,9 @@ module fake_uart(clk, reset,
      begin
 	if (r_state == 2)
 	  begin
+`ifdef debug_fake_rx
 	     $display("xxx dispense %0d %o", r_index, rdata[r_index]);
+`endif
 	     rx_data = rdata[r_index];
 	     r_index = r_index + 1;
 	  end
diff --git a/verif/test_io.v b/verif/test_io.v
index 3b2cbb2..cc59590 100644
--- a/verif/test_io.v
+++ b/verif/test_io.v
@@ -8,6 +8,7 @@
 
 `include "../verif/fake_uart.v"
 `include "../rtl/brg.v"
+
 `include "../rtl/ide_disk.v"
 `include "../rtl/ide.v"
 `include "../rtl/ram_256x12.v"
diff --git a/verif/test_pdp8.v b/verif/test_pdp8.v
index e2ae969..992deae 100644
--- a/verif/test_pdp8.v
+++ b/verif/test_pdp8.v
@@ -4,9 +4,14 @@
 
 `include "../rtl/pdp8_tt.v"
 `include "../rtl/pdp8_rf.v"
+`include "../rtl/pdp8_kw.v"
 `include "../rtl/pdp8_io.v"
 `include "../rtl/pdp8_ram.v"
 `include "../rtl/pdp8.v"
+
+`include "../verif/fake_uart.v"
+`include "../rtl/brg.v"
+
 `include "../rtl/ide_disk.v"
 `include "../rtl/ide.v"
 `include "../rtl/ram_32kx12.v"
@@ -115,7 +120,8 @@ module test;
       $timeformat(-9, 0, "ns", 7);
 
       $dumpfile("test_pdp8.vcd");
-      $dumpvars(0, test.cpu);
+//      $dumpvars(0, test.cpu);
+       $dumpvars(0, test);
     end
 
   initial
@@ -266,6 +272,7 @@ module test;
 	    $display("cpu.io_interrupt %b io.io_interrupt %b tt.io_interrupt %b",
 		     cpu.io_interrupt, 
 		     io.io_interrupt, io.tt.io_interrupt);
+	    $display("pc %o ir %o", cpu.pc, cpu.mb);
 	    $finish;
 	 end