mirror of
https://github.com/livingcomputermuseum/cpus-pdp8.git
synced 2026-01-13 15:37:04 +00:00
added rf behavioral model
This commit is contained in:
brad
parent
ee7e45a41d
commit
44fd080f1d
264
verif/NOTEs.txt
Normal file
264
verif/NOTEs.txt
Normal file
@ -0,0 +1,264 @@
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rf: DMAR ac 0000
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rf: read wc 7600
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rf: read ca 6603 (dma_addr 06604)
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rf: start! disk_addr 0000000 (000 0000) (06604 7601)
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rf: DMAR ac 0000
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rf: read wc 0000
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rf: read ca 7003 (dma_addr 07004)
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rf: start! disk_addr 0000000 (000 0000) (07004 0001)
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rf: snoop update wc 7775
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rf: snoop update ca 6621
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rf: DIML 0020
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rf: DMAR ac 0000
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 20000)
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rf: start! disk_addr 0020000 (002 0000) (20000 0001)
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rf: write wc 0000
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rf: write ca 27777
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rf: DIML 0000
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rf: DMAR ac 0000
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 00000)
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rf: start! disk_addr 0020000 (002 0000) (00000 0001)
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rf: snoop update wc 7751
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rf: snoop update ca 7751
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rf: write wc 0000
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rf: write ca 07777
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rf: DIML 0020
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rf: DMAR ac 0000
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 20000)
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rf: start! disk_addr 0020000 (002 0000) (20000 0001)
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rf: write wc 0000
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rf: write ca 27777
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rf: DIML 0010
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rf: DMAR ac 0000
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 10000)
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rf: start! disk_addr 0310000 (031 0000) (10000 0001)
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rf: write wc 0000
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rf: write ca 17777
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rf: DIML 0010
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rf: DMAR ac 0000
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 10000)
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rf: start! disk_addr 0010000 (001 0000) (10000 0001)
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rf: write wc 0000
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rf: write ca 17777
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rf: DIML 0010
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rf: DMAW ac 0000
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 10000)
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rf: start! disk_addr 0010000 (001 0000) (10000 0001)
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rf: write wc 0001
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rf: write ca 10000
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rf: done
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rf: done
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rf: done
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rf: done
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rf: set DCF (CIE 0)
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rf: DIML 0000
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rf: DMAR ac 0000
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 00000)
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rf: start! disk_addr 0030000 (003 0000) (00000 0001)
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rf: snoop update wc 7751
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rf: snoop update ca 7751
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rf: write wc 0000
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rf: write ca 07777
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rf: done
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rf: done
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rf: done
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rf: done
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rf: set DCF (CIE 0)
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rf: DIML 0010
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rf: DMAR ac 0000
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 10000)
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rf: start! disk_addr 0040000 (004 0000) (10000 0001)
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rf: write wc 0000
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rf: write ca 17777
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rf: done
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rf: done
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rf: done
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rf: done
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rf: set DCF (CIE 0)
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rf: DCMA
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-----
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rf: set DCF (CIE 1)
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rf: DCMA
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rf: DIML 0520
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rf: read wc 6000
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rf: read ca 5777 (dma_addr 26000)
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rf: start! disk_addr 0016000 (001 6000) (26000 6001)
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rf: write wc 0000
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rf: write ca 27777
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rf: done
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rf: done
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rf: done
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rf: done
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rf: set DCF (CIE 1)
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rf: DCMA
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rf: DIML 0520
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rf: DMAR ac 0000
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 20000)
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rf: start! disk_addr 0000000 (000 0000) (20000 0001)
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rf: write wc 0000
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rf: write ca 27777
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rf: done
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rf: done
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rf: done
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rf: done
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rf: set DCF (CIE 1)
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rf: DCMA
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rf: DIML 0530
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rf: DMAR ac 6000
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rf: read wc 4400
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rf: read ca 7777 (dma_addr 30000)
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rf: start! disk_addr 0446000 (044 6000) (30000 4401)
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rf: write wc 0000
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rf: write ca 33377
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rf: done
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rf: done
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rf: done
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rf: done
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rf: set DCF (CIE 1)
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rf: DCMA
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rf: DIML 0520
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rf: DMAR ac 0000
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 20000)
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rf: start! disk_addr 0010000 (001 0000) (20000 0001)
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rf: write wc 0000
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rf: write ca 27777
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rf: done
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rf: done
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rf: done
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rf: done
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rf: set DCF (CIE 1)
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rf: DCMA
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--------
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rf: read wc 6000
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rf: read ca 5777 (dma_addr 26000) 4
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 20000) 5
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rf: read wc 4400
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rf: read ca 7777 (dma_addr 30000) 6
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rf: read wc 0000
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rf: read ca 7777 (dma_addr 20000)` 7
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--------
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.R FOCALrf: ma 27777, wc 0 1
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rf: ma 25377, wc 7400 2
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rf: ma 25377, wc 7400 3
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rf: ma 25777, wc 6000 4
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rf: ma 27777, wc 0 5
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rf: ma 37777, wc 4400 6
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rf: ma 27777, wc 0 7
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rf: ma 25377, wc 7400 8
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rf: ma 33377, wc 4400 9
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rf: ma 36777, wc 7000 10
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rf: ma 25777, wc 6000 11
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.R FOCALrf: ma 27777, wc 0 1
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rf: done; ma 27777, wc 0
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rf: ma 25377, wc 7400 2
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rf: done; ma 25777, wc 0
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rf: ma 25377, wc 7400 3
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rf: done; ma 25777, wc 0
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rf: ma 25777, wc 6000 4
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rf: done; ma 27777, wc 0
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rf: ma 27777, wc 0 5
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rf: done; ma 27777, wc 0
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rf: ma 37777, wc 4400 6
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rf: done; ma 33377, wc 0
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rf: ma 27777, wc 0 7
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rf: done; ma 27777, wc 0
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rf: ma 25377, wc 7400 8
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rf: done; ma 25777, wc 0
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rf: ma 33377, wc 4400 9
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rf: done; ma 36777, wc 0
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rf: ma 36777, wc 7000 10
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rf: done; ma 37777, wc 0
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rf: ma 25777, wc 6000 11
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rf: done; ma 27777, wc 0
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---
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xxx rf_go! (rf_da 20000, wc 0, ma 7777)
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xxx rf_go! (rf_da 20000, wc 0, ma 7777)
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xxx rf_go! (rf_da 310000, wc 0, ma 7777)
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xxx rf_go! (rf_da 10000, wc 0, ma 7777)
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xxx rf_go! (rf_da 10000, wc 0, ma 7777)
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xxx rf_go! (rf_da 30000, wc 0, ma 7777)
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xxx rf_go! (rf_da 40000, wc 0, ma 7777)
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xxx rf_go! (rf_da 0, wc 0, ma 7777)
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xxx rf_go! (rf_da 10000, wc 0, ma 7777)
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xxx rf_go! (rf_da 310000, wc 7400, ma 5377)
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xxx rf_go! (rf_da 16000, wc 6000, ma 5777)
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xxx rf_go! (rf_da 0, wc 0, ma 7777)
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xxx rf_go! (rf_da 10000, wc 0, ma 7777)
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xxx rf_go! (rf_da 310400, wc 7400, ma 5377)
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xxx rf_go! (rf_da 376000, wc 7400, ma 5377)
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xxx rf_go! (rf_da 16000, wc 6000, ma 5777)
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xxx rf_go! (rf_da 0, wc 0, ma 7777)
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xxx rf_go! (rf_da 446000, wc 4400, ma 7777)
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xxx rf_go! (rf_da 10000, wc 0, ma 7777)
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xxx rf_go! (rf_da 376000, wc 7400, ma 5377)
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xxx rf_go! (rf_da 451400, wc 4400, ma 3377)
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xxx rf_go! (rf_da 455000, wc 7000, ma 6777)
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xxx rf_go! (rf_da 16000, wc 6000, ma 5777)
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------
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rf: read dma to 06603, count 7600; disk_addr 0 (0) EMA 0 DMA 0
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rf: read dma to 07003, count 0; disk_addr 0 (0) EMA 0 DMA 0
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rf: read dma to 27777, count 0; disk_addr 20000 (8192) EMA 2 DMA 0
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rf: read dma to 07777, count 0; disk_addr 20000 (8192) EMA 2 DMA 0
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rf: read dma to 27777, count 0; disk_addr 20000 (8192) EMA 2 DMA 0
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rf: read dma to 17777, count 0; disk_addr 310000 (102400) EMA 31 DMA 0
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rf: read dma to 17777, count 0; disk_addr 10000 (4096) EMA 1 DMA 0
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rf: write dma to 17777, count 0; disk_addr 10000 (4096) EMA 1 DMA 0
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rf: read dma to 07777, count 0; disk_addr 30000 (12288) EMA 3 DMA 0
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rf: read dma to 17777, count 0; disk_addr 40000 (16384) EMA 4 DMA 0
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xxx boom 1; cycles 110000
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xxx boom 2; cycles 120000
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xxx boom 3; cycles 200000
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rf: read dma to 27777, count 0; disk_addr 0 (0) EMA 0 DMA 0
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rf: read dma to 27777, count 0; disk_addr 10000 (4096) EMA 1 DMA 0
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rf: read dma to 25377, count 7400; disk_addr 310000 (102400) EMA 31 DMA 0
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rf: write dma to 25777, count 6000; disk_addr 16000 (7168) EMA 1 DMA 6000
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rf: read dma to 27777, count 0; disk_addr 0 (0) EMA 0 DMA 0
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xxx boom 4; cycles 1000000
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rf: read dma to 27777, count 0; disk_addr 10000 (4096) EMA 1 DMA 0
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rf: read dma to 25377, count 7400; disk_addr 310400 (102656) EMA 31 DMA 400
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rf: read dma to 25377, count 7400; disk_addr 376000 (130048) EMA 37 DMA 6000
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rf: write dma to 25777, count 6000; disk_addr 16000 (7168) EMA 1 DMA 6000
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rf: read dma to 27777, count 0; disk_addr 0 (0) EMA 0 DMA 0
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rf: read dma to 37777, count 4400; disk_addr 446000 (150528) EMA 44 DMA 6000
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rf: read dma to 27777, count 0; disk_addr 10000 (4096) EMA 1 DMA 0
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rf: read dma to 25377, count 7400; disk_addr 376000 (130048) EMA 37 DMA 6000
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rf: read dma to 33377, count 4400; disk_addr 451400 (152320) EMA 45 DMA 1400
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rf: read dma to 36777, count 7000; disk_addr 455000 (154112) EMA 45 DMA 5000
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rf: write dma to 25777, count 6000; disk_addr 16000 (7168) EMA 1 DMA 6000
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xxx boom 5; cycles 1100000
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64
verif/fake_ram.v
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64
verif/fake_ram.v
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@ -0,0 +1,64 @@
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module fake_ram(clk, reset,
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ram_read_req, ram_write_req, ram_done,
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ram_ma, ram_in, ram_out);
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input clk;
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input reset;
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input ram_read_req;
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input ram_write_req;
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output ram_done;
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input [14:0] ram_ma;
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input [11:0] ram_in;
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output [11:0] ram_out;
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//--------------
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reg [11:0] ram [0:32767];
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integer i;
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integer ram_debug;
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initial
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begin
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ram_debug = 0;
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for (i = 0; i < 32768; i=i+1)
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ram[i] = 12'b0;
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end
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reg [2:0] ram_state;
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wire [2:0] ram_state_next;
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always @(posedge clk)
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if (reset)
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ram_state <= 0;
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else
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ram_state <= ram_state_next;
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assign ram_state_next =
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(ram_state == 0 && ram_read_req) ? 1 :
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(ram_state == 1) ? 0 :
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(ram_state == 0 && ram_write_req) ? 2 :
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(ram_state == 2) ? 0 :
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0;
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assign ram_done = ram_state == 1 || ram_state == 2;
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always @(ram_state)
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begin
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if (ram_state == 2)
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begin
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if (ram_debug) $display("ram: write [%o] <- %o", ram_ma, ram_in);
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ram[ ram_ma ] = ram_in;
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end
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if (ram_state == 1)
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begin
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if (ram_debug) $display("ram: read [%o] -> %o", ram_ma, ram[ram_ma]);
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end
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end
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assign ram_out = ram[ ram_ma ];
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endmodule
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@ -5,12 +5,13 @@
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//`define debug_fake_tx 1
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`define debug_fake_rx 1
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module fake_uart(clk, reset,
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module fake_uart(clk, reset, state,
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tx_clk, tx_req, tx_ack, tx_data, tx_empty,
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rx_clk, rx_req, rx_ack, rx_empty, rx_data);
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input clk;
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input reset;
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input [3:0] state;
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input tx_clk;
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input tx_req;
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@ -47,17 +48,25 @@ module fake_uart(clk, reset,
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assign tx_empty = t_delay == 0;
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initial
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t_delay = 0;
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begin
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t_delay = 0;
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refire_state = 0;
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end
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always @(posedge clk)
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begin
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if (t_state == 1)
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t_delay = 20;
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begin
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t_delay = 20;
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end
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if (t_delay > 0)
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begin
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t_delay = t_delay - 1;
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if (t_delay == 0)
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t_done = 1;
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begin
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t_done = 1;
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//$display("xxx t_done; cycles %d", cycles);
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end
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`ifdef debug_fake_tx
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$display("t_state %d t_delay %d", t_state, t_delay);
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`endif
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@ -66,7 +75,97 @@ module fake_uart(clk, reset,
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t_done = 0;
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end
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integer cycles;
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initial
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cycles = 0;
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always @(posedge clk)
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begin
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if (state == 4'b0001)
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begin
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cycles = cycles + 1;
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//$display("cycles %d", cycles);
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// if (r_index == r_count && cycles >= 30000)
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// begin
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// $display("xxx want input; cycles %d", cycles);
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// end
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if (r_index == r_count && cycles == 200000)
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begin
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rdata[0] = "L";
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rdata[1] = "O";
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rdata[2] = "G";
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rdata[3] = "I";
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rdata[4] = "N";
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rdata[5] = " ";
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rdata[6] = "2";
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rdata[7] = " ";
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rdata[8] = "L";
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rdata[9] = "X";
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rdata[10] = "H";
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rdata[11] = "E";
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rdata[12] = "\215";
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rdata[13] = "\215";
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r_index = 0;
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r_count = 14;
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r_refires = 1;
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$display("xxx boom 1; cycles %d", cycles);
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end
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if (r_index == r_count && cycles == 300000)
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begin
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rdata[0] = "\215";
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r_index = 0;
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r_count = 1;
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r_refires = 2;
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$display("xxx boom 2; cycles %d", cycles);
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end
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if (r_index == r_count && cycles == 400000)
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begin
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rdata[0] = "\215";
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r_index = 0;
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r_count = 1;
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r_refires = 3;
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$display("xxx boom 3; cycles %d", cycles);
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end
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//`define msg_rcat 1
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`define msg_rfocal 1
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if (r_index == r_count && cycles == 500000)
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begin
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`ifdef msg_rcat
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rdata[0] = "R";
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rdata[1] = " ";
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rdata[2] = "C";
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rdata[3] = "A";
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rdata[4] = "T";
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rdata[5] = "\215";
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r_index = 0;
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r_count = 6;
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`endif
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`ifdef msg_rfocal
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rdata[0] = "R";
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rdata[1] = " ";
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rdata[2] = "F";
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rdata[3] = "O";
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rdata[4] = "C";
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rdata[5] = "A";
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rdata[6] = "L";
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rdata[7] = "\215";
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r_index = 0;
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r_count = 8;
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`endif
|
||||
r_refires = 4;
|
||||
$display("xxx boom 4; cycles %d", cycles);
|
||||
end
|
||||
if (r_index == r_count && cycles == 600000)
|
||||
begin
|
||||
rdata[0] = "\215";
|
||||
r_index = 0;
|
||||
r_count = 1;
|
||||
r_refires = 5;
|
||||
$display("xxx boom 5; cycles %d", cycles);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//
|
||||
assign r_state_next =
|
||||
r_state == 0 && rx_req ? 1 :
|
||||
@ -77,45 +176,53 @@ module fake_uart(clk, reset,
|
||||
|
||||
assign rx_ack = r_state == 1;
|
||||
|
||||
integer r_index, r_count;
|
||||
integer r_index, r_count, r_refires;
|
||||
|
||||
integer do_refire, refire_state;
|
||||
|
||||
assign rx_empty = r_index == r_count;
|
||||
|
||||
initial
|
||||
begin
|
||||
r_index= 0;
|
||||
r_count = 23;
|
||||
`ifdef no_fake_input
|
||||
r_count = 0;
|
||||
`else
|
||||
r_count = 22;
|
||||
`endif
|
||||
r_refires = 0;
|
||||
end
|
||||
|
||||
reg [7:0] rdata[23:0];
|
||||
reg [7:0] rdata[50:0];
|
||||
integer ii;
|
||||
|
||||
/* "START\r01:01:85\r10:10\r\r\r" */
|
||||
/* "START\r01:01:85\r10:10\r" */
|
||||
initial
|
||||
begin
|
||||
rdata[0] = "S";
|
||||
rdata[1] = "T";
|
||||
rdata[2] = "A";
|
||||
rdata[3] = "R";
|
||||
rdata[4] = "T";
|
||||
rdata[5] = "\015";
|
||||
rdata[6] = "0";
|
||||
rdata[7] = "1";
|
||||
rdata[8] = ":";
|
||||
rdata[9] = "0";
|
||||
rdata[10] = "1";
|
||||
rdata[11] = ":";
|
||||
rdata[12] = "8";
|
||||
rdata[13] = "5";
|
||||
rdata[14] = "\015";
|
||||
rdata[15] = "1";
|
||||
rdata[16] = "0";
|
||||
rdata[17] = ":";
|
||||
rdata[18] = "1";
|
||||
rdata[19] = "0";
|
||||
rdata[20] = "\015";
|
||||
rdata[21] = "\015";
|
||||
rdata[22] = "\015";
|
||||
|
||||
ii = 0;
|
||||
rdata[ii] = 0; ii=ii+1;
|
||||
rdata[ii] = "S"; ii=ii+1;
|
||||
rdata[ii] = "T"; ii=ii+1;
|
||||
rdata[ii] = "A"; ii=ii+1;
|
||||
rdata[ii] = "R"; ii=ii+1;
|
||||
rdata[ii] = "T"; ii=ii+1;
|
||||
rdata[ii] = "\215"; ii=ii+1;
|
||||
rdata[ii] = "0"; ii=ii+1;
|
||||
rdata[ii] = "1"; ii=ii+1;
|
||||
rdata[ii] = ":"; ii=ii+1;
|
||||
rdata[ii] = "0"; ii=ii+1;
|
||||
rdata[ii] = "1"; ii=ii+1;
|
||||
rdata[ii] = ":"; ii=ii+1;
|
||||
rdata[ii] = "8"; ii=ii+1;
|
||||
rdata[ii] = "5"; ii=ii+1;
|
||||
rdata[ii] = "\215"; ii=ii+1;
|
||||
rdata[ii] = "1"; ii=ii+1;
|
||||
rdata[ii] = "0"; ii=ii+1;
|
||||
rdata[ii] = ":"; ii=ii+1;
|
||||
rdata[ii] = "1"; ii=ii+1;
|
||||
rdata[ii] = "0"; ii=ii+1;
|
||||
rdata[ii] = "\215"; ii=ii+1;
|
||||
|
||||
rx_data = 0;
|
||||
end
|
||||
|
||||
@ -125,13 +232,13 @@ module fake_uart(clk, reset,
|
||||
if (r_state == 2)
|
||||
begin
|
||||
`ifdef debug_fake_rx
|
||||
$display("xxx dispense %0d %o", r_index, rdata[r_index]);
|
||||
$display("xxx dispense %0d %o %t",
|
||||
r_index, rdata[r_index], $time);
|
||||
`endif
|
||||
rx_data = rdata[r_index];
|
||||
r_index = r_index + 1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
always @(posedge clk)
|
||||
|
||||
@ -127,9 +127,9 @@ module ram_s3board(ram_a, ram_oe_n, ram_we_n,
|
||||
ram1_ce_n, ram1_ub_n, ram1_lb_n, ram_we_n, ram_oe_n);
|
||||
|
||||
if (ram_oe_n == 0 && ram_we_n == 1)
|
||||
$display("ram_s3board: read [%o] -> %o", ram_a, ram1_io);
|
||||
$display("ram_s3board: read [%o] -> %o %t", ram_a, ram1_io, $time);
|
||||
if (ram_oe_n == 1 && ram_we_n == 0)
|
||||
$display("ram_s3board: write [%o] <- %o", ram_a, ram1_io);
|
||||
$display("ram_s3board: write [%o] <- %o %t", ram_a, ram1_io, $time);
|
||||
end
|
||||
`endif
|
||||
|
||||
|
||||
41
verif/run.sh
41
verif/run.sh
@ -1,4 +1,43 @@
|
||||
cver +showpc +cycles=500000 +test=tss8_init.mem +pc=24200 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v >xx
|
||||
../cver/gplcver-2.12a.src/bin/cver \
|
||||
+loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap \
|
||||
+showpc \
|
||||
+cycles=2000000 \
|
||||
+pc=07400 \
|
||||
test_pdp8.v
|
||||
exit 0
|
||||
|
||||
../cver/gplcver-2.12a.src/bin/cver \
|
||||
+loadvpi=../pli/rf/pli_rf.so:vpi_compat_bootstrap \
|
||||
+showpc \
|
||||
+cycles=2000000 \
|
||||
+pc=07400 \
|
||||
test_pdp8.v
|
||||
exit 0
|
||||
|
||||
# +loadvpi=../pli/disassemble/pli_disassemble.so:vpi_compat_bootstrap \
|
||||
#
|
||||
|
||||
cver \
|
||||
+loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap \
|
||||
+loadvpi=../pli/disassemble/pli_disassemble.so:vpi_compat_bootstrap \
|
||||
+showpc \
|
||||
+cycles=2000000 \
|
||||
+pc=07400 \
|
||||
test_pdp8.v
|
||||
exit 0
|
||||
|
||||
cver \
|
||||
+loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap \
|
||||
+test=../tests/basic/user.mem +pc=0400 \
|
||||
+showpc \
|
||||
+cycles=100 \
|
||||
+define+no_fake_input=1 \
|
||||
test_pdp8.v
|
||||
exit 0
|
||||
|
||||
|
||||
# +test=tss8_init.mem +pc=24200 \
|
||||
#
|
||||
|
||||
#cver +showpc +test=../tests/diags/MAINDEC-08-D5FA.mem +pc=0150 +switches=0000 +cycles=200000 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v >zz
|
||||
|
||||
|
||||
5
verif/runtest.sh
Executable file
5
verif/runtest.sh
Executable file
@ -0,0 +1,5 @@
|
||||
../cver/gplcver-2.12a.src/bin/cver \
|
||||
+loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap \
|
||||
test_rf.v
|
||||
exit 0
|
||||
|
||||
@ -11,12 +11,16 @@
|
||||
`endif
|
||||
|
||||
`ifdef sim
|
||||
`define use_fake_uart
|
||||
`define debug
|
||||
`define sim_time
|
||||
//`define debug_s3ram
|
||||
`define debug_s3ram
|
||||
//`define use_sim_ram_model
|
||||
//`define debug_vcd
|
||||
//`define debug_log
|
||||
`endif
|
||||
|
||||
//`define use_sim_ram_model
|
||||
//`define use_rf_pli
|
||||
|
||||
`include "../rtl/pdp8_tt.v"
|
||||
`include "../rtl/pdp8_rf.v"
|
||||
@ -48,6 +52,8 @@ module test;
|
||||
reg [11:0] switches;
|
||||
|
||||
wire [14:0] initial_pc;
|
||||
wire [11:0] pc_out;
|
||||
wire [11:0] ac_out;
|
||||
|
||||
wire [11:0] ram_data_in;
|
||||
wire ram_rd;
|
||||
@ -92,10 +98,12 @@ module test;
|
||||
|
||||
reg rs232_in;
|
||||
wire rs232_out;
|
||||
|
||||
|
||||
pdp8 cpu(.clk(clk),
|
||||
.reset(reset),
|
||||
.initial_pc(initial_pc),
|
||||
.pc_out(pc_out),
|
||||
.ac_out(ac_out),
|
||||
.ram_addr(ram_addr),
|
||||
.ram_data_in(ram_data_out),
|
||||
.ram_data_out(ram_data_in),
|
||||
@ -146,6 +154,7 @@ module test;
|
||||
.rs232_in(rs232_in),
|
||||
.rs232_out(rs232_out));
|
||||
|
||||
`ifndef use_rf_pli
|
||||
pdp8_ram ram(.clk(clk),
|
||||
.reset(reset),
|
||||
.addr(ram_addr),
|
||||
@ -159,7 +168,8 @@ module test;
|
||||
.sram1_ub_n(sram1_ub_n), .sram1_lb_n(sram1_lb_n),
|
||||
.sram2_io(sram2_io), .sram2_ce_n(sram2_ce_n),
|
||||
.sram2_ub_n(sram2_ub_n), .sram2_lb_n(sram2_lb_n));
|
||||
|
||||
`endif
|
||||
|
||||
`ifndef use_sim_model
|
||||
ram_s3board sram(.ram_a(sram_a),
|
||||
.ram_oe_n(sram_oe_n),
|
||||
@ -179,13 +189,21 @@ module test;
|
||||
|
||||
assign initial_pc = starting_pc;
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
$timeformat(-9, 0, "ns", 7);
|
||||
|
||||
`ifdef debug_log
|
||||
`else
|
||||
`ifdef __CVER__
|
||||
$nolog;
|
||||
`endif
|
||||
`endif
|
||||
|
||||
`ifdef debug_vcd
|
||||
$dumpfile("test_pdp8.vcd");
|
||||
$dumpvars(0, test);
|
||||
`endif
|
||||
end
|
||||
|
||||
initial
|
||||
@ -194,7 +212,7 @@ module test;
|
||||
clk = 0;
|
||||
reset = 0;
|
||||
switches = 0;
|
||||
rs232_in = 0;
|
||||
rs232_in = 1;
|
||||
|
||||
max_cycles = 0;
|
||||
max_cycles = 100;
|
||||
@ -323,6 +341,12 @@ module test;
|
||||
cpu.l, cpu.ac, cpu.interrupt_enable,
|
||||
cpu.IF, cpu.DF, cpu.UF, cpu.SF, cpu.IB, cpu.UB,
|
||||
cpu.interrupt_inhibit_delay);
|
||||
|
||||
`ifdef xxx
|
||||
if (show_one_pc)
|
||||
#1 $pli_disassemble(cpu.pc, cpu.mb);
|
||||
`endif
|
||||
|
||||
show_one_pc = 0;
|
||||
end
|
||||
|
||||
@ -358,10 +382,19 @@ module test;
|
||||
end
|
||||
end
|
||||
|
||||
`ifndef use_rf_pli
|
||||
always @(posedge clk)
|
||||
begin
|
||||
$pli_ide(ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da);
|
||||
end
|
||||
`endif
|
||||
|
||||
`ifdef use_rf_pli
|
||||
always @(reset /*or ram_addr or ram_data_in*/ or ram_rd or ram_wr)
|
||||
begin
|
||||
$pli_ram(reset, ram_addr, ram_data_in, ram_data_out, ram_rd, ram_wr);
|
||||
end
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
372
verif/test_rf.v
372
verif/test_rf.v
@ -2,14 +2,20 @@
|
||||
// testing top end for pdp8_rf.v
|
||||
//
|
||||
|
||||
`define debug 1
|
||||
|
||||
`include "../rtl/pdp8_rf.v"
|
||||
`include "../rtl/ide_disk.v"
|
||||
`include "../rtl/ide.v"
|
||||
`include "../rtl/ram_256x12.v"
|
||||
`include "../verif/fake_ide.v"
|
||||
`include "../verif/fake_ram.v"
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
`ifdef use_fake_ide
|
||||
`include "../verif/fake_ide.v"
|
||||
`endif
|
||||
|
||||
module test;
|
||||
|
||||
reg clk, reset;
|
||||
@ -21,11 +27,11 @@ module test;
|
||||
|
||||
wire ram_read_req;
|
||||
wire ram_write_req;
|
||||
reg ram_done;
|
||||
wire ram_done;
|
||||
|
||||
wire [14:0] ram_ma;
|
||||
wire [11:0] ram_out;
|
||||
reg [11:0] ram_in;
|
||||
wire [11:0] ram_in;
|
||||
|
||||
reg [5:0] io_select;
|
||||
reg [11:0] io_data_in;
|
||||
@ -39,11 +45,13 @@ module test;
|
||||
wire [2:0] ide_da;
|
||||
wire [15:0] ide_data_bus;
|
||||
|
||||
`ifdef use_fake_ide
|
||||
fake_ide ide(.ide_dior(ide_dior),
|
||||
.ide_diow(ide_diow),
|
||||
.ide_cs(ide_cs),
|
||||
.ide_da(ide_da),
|
||||
.ide_data_bus(ide_data_bus));
|
||||
`endif
|
||||
|
||||
pdp8_rf rf(.clk(clk),
|
||||
.reset(reset),
|
||||
@ -53,9 +61,11 @@ module test;
|
||||
.io_data_in(io_data_in),
|
||||
.io_data_out(io_data_out),
|
||||
.io_select(io_select),
|
||||
.io_selected(io_selected),
|
||||
.io_data_avail(io_data_avail),
|
||||
.io_interrupt(io_interrupt),
|
||||
.io_skip(io_skip),
|
||||
.io_clear_ac(io_clear_ac),
|
||||
.ram_read_req(ram_read_req),
|
||||
.ram_write_req(ram_write_req),
|
||||
.ram_done(ram_done),
|
||||
@ -68,6 +78,58 @@ module test;
|
||||
.ide_da(ide_da),
|
||||
.ide_data_bus(ide_data_bus));
|
||||
|
||||
fake_ram ram(.clk(clk),
|
||||
.reset(reset),
|
||||
.ram_read_req(ram_read_req),
|
||||
.ram_write_req(ram_write_req),
|
||||
.ram_done(ram_done),
|
||||
.ram_ma(ram_ma),
|
||||
.ram_in(ram_out),
|
||||
.ram_out(ram_in));
|
||||
|
||||
|
||||
//
|
||||
task write_ram;
|
||||
input [14:0] addr;
|
||||
input [11:0] data;
|
||||
|
||||
begin
|
||||
@(posedge clk);
|
||||
force ram_ma = addr;
|
||||
force ram_out = data;
|
||||
force ram_write_req = 1;
|
||||
@(posedge clk);
|
||||
force ram_write_req = 0;
|
||||
@(posedge clk);
|
||||
release ram_ma;
|
||||
release ram_out;
|
||||
release ram_write_req;
|
||||
@(posedge clk);
|
||||
end
|
||||
endtask
|
||||
|
||||
//
|
||||
task read_ram;
|
||||
input [14:0] addr;
|
||||
output [11:0] data;
|
||||
|
||||
begin
|
||||
@(posedge clk);
|
||||
force ram_ma = addr;
|
||||
force ram_read_req = 1;
|
||||
@(posedge clk);
|
||||
begin
|
||||
data = ram_in;
|
||||
force ram_read_req = 0;
|
||||
end
|
||||
@(posedge clk);
|
||||
release ram_ma;
|
||||
release ram_read_req;
|
||||
@(posedge clk);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
//
|
||||
task write_rf_reg;
|
||||
input [11:0] isn;
|
||||
@ -119,6 +181,173 @@ module test;
|
||||
end
|
||||
endtask
|
||||
|
||||
//
|
||||
task read_rf_skip;
|
||||
input [11:0] isn;
|
||||
output skip;
|
||||
|
||||
begin
|
||||
@(posedge clk);
|
||||
begin
|
||||
state = 4'h0;
|
||||
mb_in = isn;
|
||||
io_select = isn[8:3];
|
||||
io_data_in = 0;
|
||||
iot = 1;
|
||||
end
|
||||
@(posedge clk);
|
||||
state = 4'h1;
|
||||
@(posedge clk);
|
||||
begin
|
||||
skip = io_skip;
|
||||
state = 4'h2;
|
||||
end
|
||||
@(posedge clk);
|
||||
state = 4'h3;
|
||||
@(posedge clk);
|
||||
begin
|
||||
state = 4'h0;
|
||||
iot = 0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
//
|
||||
task wait_for_rf;
|
||||
begin
|
||||
while (rf.DCF == 1'b0)
|
||||
begin
|
||||
@(posedge clk);
|
||||
begin
|
||||
state = 4'h0;
|
||||
mb_in = 0;
|
||||
io_select = 0;
|
||||
io_data_in = 0;
|
||||
iot = 0;
|
||||
end
|
||||
@(posedge clk);
|
||||
state = 4'h1;
|
||||
@(posedge clk);
|
||||
state = 4'h2;
|
||||
@(posedge clk);
|
||||
state = 4'h3;
|
||||
@(posedge clk);
|
||||
state = 4'h0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task clear_ram;
|
||||
integer a;
|
||||
begin
|
||||
ram.ram_debug = 0;
|
||||
for (a = 0; a <= 12'o7777; a = a + 1)
|
||||
write_ram(a, 0);
|
||||
//ram.ram_debug = 1;
|
||||
end
|
||||
endtask
|
||||
|
||||
task failure;
|
||||
input [14:0] addr;
|
||||
input [11:0] got;
|
||||
input [11:0] expected;
|
||||
|
||||
begin
|
||||
$display("FAILURE addr %o, read %o, expected %o",
|
||||
addr, got, expected);
|
||||
$finish;
|
||||
end
|
||||
endtask
|
||||
|
||||
task fill_ram;
|
||||
input [14:0] addr;
|
||||
input [11:0] value;
|
||||
input count;
|
||||
|
||||
integer count;
|
||||
integer a;
|
||||
begin
|
||||
for (a = addr; count > 0; a = a + 1)
|
||||
begin
|
||||
write_ram(a, value);
|
||||
count = count - 1;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task check_ram;
|
||||
input [14:0] addr;
|
||||
input [11:0] value;
|
||||
integer a;
|
||||
reg [11:0] rv;
|
||||
|
||||
begin
|
||||
read_ram(addr, rv);
|
||||
$display("check_ram: %o %o @ %o", rv, value, addr);
|
||||
if (rv != value)
|
||||
failure(addr, rv, value);
|
||||
end
|
||||
endtask
|
||||
|
||||
task check_fill_ram;
|
||||
input [14:0] addr;
|
||||
input [11:0] value;
|
||||
input count;
|
||||
integer count;
|
||||
integer a;
|
||||
reg [11:0] rv;
|
||||
|
||||
begin
|
||||
for (a = addr; count > 0; a = a + 1)
|
||||
begin
|
||||
read_ram(a, rv);
|
||||
if (rv != value)
|
||||
failure(a, rv, value);
|
||||
count = count - 1;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task write_rf;
|
||||
input [17:0] da;
|
||||
input [14:0] ma;
|
||||
input count;
|
||||
integer count;
|
||||
|
||||
reg [11:0] cw;
|
||||
|
||||
begin
|
||||
cw = -count;
|
||||
write_ram(14'o07750, cw); // word count
|
||||
write_ram(14'o07751, ma[11:0]-1); // current addr
|
||||
|
||||
write_rf_reg(12'o6615, {6'b0, ma[14:12], 3'b0}); // DIML
|
||||
write_rf_reg(12'o6643, {6'b0, da[17:12]}); // DXAL
|
||||
write_rf_reg(12'o6605, da[11:0]); // DMAW
|
||||
wait_for_rf;
|
||||
end
|
||||
endtask
|
||||
|
||||
task read_rf;
|
||||
input [17:0] da;
|
||||
input [14:0] ma;
|
||||
input count;
|
||||
integer count;
|
||||
|
||||
reg [11:0] cw;
|
||||
|
||||
begin
|
||||
cw = -count;
|
||||
write_ram(14'o07750, cw);
|
||||
write_ram(14'o07751, ma[11:0]-1);
|
||||
|
||||
write_rf_reg(12'o6615, {6'b0, ma[14:12], 3'b0}); // DIML
|
||||
write_rf_reg(12'o6643, {6'b0, da[17:12]}); // DXAL
|
||||
write_rf_reg(12'o6603, da[11:0]); // DMAR
|
||||
wait_for_rf;
|
||||
end
|
||||
endtask
|
||||
|
||||
initial
|
||||
begin
|
||||
$timeformat(-9, 0, "ns", 7);
|
||||
@ -127,38 +356,133 @@ module test;
|
||||
$dumpvars(0, test.rf);
|
||||
end
|
||||
|
||||
reg [11:0] data;
|
||||
reg [11:0] data;
|
||||
integer a;
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 0;
|
||||
reset = 0;
|
||||
ram_done = 1;
|
||||
ram_in = 0;
|
||||
|
||||
#1 begin
|
||||
reset = 1;
|
||||
end
|
||||
#1 reset = 1;
|
||||
#50 reset = 0;
|
||||
|
||||
#50 begin
|
||||
reset = 0;
|
||||
end
|
||||
//---
|
||||
$display("* sanity");
|
||||
clear_ram;
|
||||
fill_ram(14'o00000, 12'o1111, 8);
|
||||
check_fill_ram(14'o00000, 12'o1111, 8);
|
||||
check_fill_ram(14'o00010, 12'o0000, 512);
|
||||
check_fill_ram(14'o01010, 12'o0000, 512);
|
||||
|
||||
write_rf_reg(12'o6000, 12'o0000);
|
||||
write_rf_reg(12'o6601, 12'o0000);
|
||||
write_rf_reg(12'o6611, 12'o0000);
|
||||
write_rf_reg(12'o6615, 12'o0000);
|
||||
write_rf_reg(12'o6641, 12'o0000);
|
||||
write_rf_reg(12'o6643, 12'o0000);
|
||||
read_rf_reg(12'o6616, data);
|
||||
`ifdef xxx
|
||||
//---
|
||||
$display("* prep");
|
||||
clear_ram;
|
||||
write_rf(18'o000000, 14'o00000, 4096);
|
||||
write_rf(18'o010000, 14'o00000, 4096);
|
||||
write_rf(18'o020000, 14'o00000, 4096);
|
||||
write_rf(18'o030000, 14'o00000, 4096);
|
||||
write_rf(18'o040000, 14'o00000, 4096);
|
||||
write_rf(18'o050000, 14'o00000, 4096);
|
||||
write_rf(18'o060000, 14'o00000, 4096);
|
||||
write_rf(18'o070000, 14'o00000, 4096);
|
||||
`endif
|
||||
|
||||
`ifdef xxx
|
||||
//---
|
||||
$display("* write 8 words; cached");
|
||||
clear_ram;
|
||||
fill_ram(14'o00000, 12'o1111, 8);
|
||||
write_rf(18'o000000, 14'o00000, 8);
|
||||
clear_ram;
|
||||
read_rf (18'o000000, 14'o01000, 8);
|
||||
check_fill_ram(14'o00000, 12'o0000, 512);
|
||||
check_fill_ram(14'o01000, 12'o1111, 8);
|
||||
check_fill_ram(14'o01010, 12'o0000, 512);
|
||||
|
||||
write_rf_reg(12'o6603, 12'o0000); // DMAR
|
||||
write_rf_reg(12'o6000, 12'o0000);
|
||||
write_rf_reg(12'o6000, 12'o0000);
|
||||
|
||||
#40000 $finish;
|
||||
//---
|
||||
$display("* write 8 words; force write");
|
||||
clear_ram;
|
||||
read_rf (18'o010000, 14'o00000, 8);
|
||||
|
||||
//---
|
||||
$display("* write 8 words; cached");
|
||||
clear_ram;
|
||||
fill_ram(14'o00000, 12'o2222, 8);
|
||||
write_rf(18'o010000, 14'o00000, 8);
|
||||
clear_ram;
|
||||
read_rf (18'o010000, 14'o00000, 8);
|
||||
check_fill_ram(14'o00000, 12'o2222, 8);
|
||||
check_fill_ram(14'o00010, 12'o0000, 512);
|
||||
read_rf (18'o000000, 14'o00000, 8);
|
||||
|
||||
//----
|
||||
$display("* read/write 2 fields");
|
||||
clear_ram;
|
||||
fill_ram(14'o10000, 12'o3333, 4096);
|
||||
write_rf(18'o000000, 14'o10000, 4032);
|
||||
write_rf(18'o010000, 14'o00000, 4096);
|
||||
read_rf (18'o000000, 14'o00000, 4032);
|
||||
read_rf (18'o010000, 14'o10000, 4096);
|
||||
$display("** checking");
|
||||
check_fill_ram(14'o00000, 12'o3333, 4032);
|
||||
check_fill_ram(14'o10000, 12'o0000, 4096);
|
||||
`endif
|
||||
|
||||
//----
|
||||
$display("* read/write individual words");
|
||||
clear_ram;
|
||||
read_rf (18'o000000, 14'o00000, 256);
|
||||
write_ram(14'o00200, 12'o0000);
|
||||
write_ram(14'o00201, 12'o1010);
|
||||
write_ram(14'o00202, 12'o2020);
|
||||
write_ram(14'o00203, 12'o3030);
|
||||
$display("** write 4");
|
||||
// rf.buffer.ram_debug = 1;
|
||||
write_rf(18'o000200, 14'o00200, 4);
|
||||
// rf.buffer.ram_debug = 0;
|
||||
$display("** read to flush");
|
||||
read_rf (18'o010000, 14'o10000, 256);
|
||||
$display("** checking");
|
||||
clear_ram;
|
||||
read_rf (18'o000000, 14'o00000, 512);
|
||||
check_ram(14'o00200, 12'o0000);
|
||||
check_ram(14'o00201, 12'o1010);
|
||||
check_ram(14'o00202, 12'o2020);
|
||||
check_ram(14'o00203, 12'o3030);
|
||||
|
||||
//----
|
||||
$display("* read/write individual words");
|
||||
clear_ram;
|
||||
read_rf (18'o000000, 14'o00000, 4032);
|
||||
write_ram(14'o00204, 12'o4040);
|
||||
write_ram(14'o00205, 12'o5050);
|
||||
write_ram(14'o00206, 12'o6060);
|
||||
write_ram(14'o00207, 12'o7070);
|
||||
write_rf(18'o000204, 14'o00204, 4);
|
||||
read_rf (18'o010000, 14'o10000, 4096);
|
||||
$display("** checking");
|
||||
clear_ram;
|
||||
read_rf (18'o000000, 14'o00000, 4032);
|
||||
check_ram(14'o00200, 12'o0000);
|
||||
check_ram(14'o00201, 12'o1010);
|
||||
check_ram(14'o00202, 12'o2020);
|
||||
check_ram(14'o00203, 12'o3030);
|
||||
check_ram(14'o00204, 12'o4040);
|
||||
check_ram(14'o00205, 12'o5050);
|
||||
check_ram(14'o00206, 12'o6060);
|
||||
check_ram(14'o00207, 12'o7070);
|
||||
$finish;
|
||||
end
|
||||
|
||||
`ifndef use_fake_ide
|
||||
always @(posedge clk)
|
||||
begin
|
||||
$pli_ide(ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da);
|
||||
end
|
||||
`endif
|
||||
|
||||
always
|
||||
begin
|
||||
#10 clk = 0;
|
||||
|
||||
8
verif/tss8.cmd
Normal file
8
verif/tss8.cmd
Normal file
@ -0,0 +1,8 @@
|
||||
load ../tss8/tss8_init.bin
|
||||
set rf enabled
|
||||
set df disabled
|
||||
attach rf rf.dsk
|
||||
run 24200
|
||||
exit
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user