diff --git a/xilinx/pdp8/.lso b/xilinx/pdp8/.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/xilinx/pdp8/.lso @@ -0,0 +1 @@ +work diff --git a/xilinx/pdp8/__ISE_repository_pdp8.ise_.lock b/xilinx/pdp8/__ISE_repository_pdp8.ise_.lock new file mode 100644 index 0000000..b4f882d Binary files /dev/null and b/xilinx/pdp8/__ISE_repository_pdp8.ise_.lock differ diff --git a/xilinx/pdp8/_xmsgs/xst.xmsgs b/xilinx/pdp8/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..183d636 --- /dev/null +++ b/xilinx/pdp8/_xmsgs/xst.xmsgs @@ -0,0 +1,97 @@ + + + +"../../rtl/pdp8.v" line 763: Ignored duplicate item in case statement. + + +"../../rtl/pdp8.v" line 799: Parameter 2 is not constant in call of system task $display. + + +"../../rtl/pdp8_tt.v" line 142: Parameter 2 is not constant in call of system task $display. + + +"../../rtl/pdp8_tt.v" line 118: The signals <io_data_in, iot, io_select, mb, rx_data> are missing in the sensitivity list of always block. + + +"../../rtl/pdp8_tt.v" line 211: Parameter 2 is not constant in call of system task $display. + + +"../../rtl/pdp8_rf.v" line 575: Parameter 2 is not constant in call of system task $display. + + +"../../rtl/pdp8_rf.v" line 557: The signals <io_data_in, iot, io_select, mb, disk_addr, PCA, DRE, EIE, PIE, CIE, MEX, DMA, EMA> are missing in the sensitivity list of always block. + + +"../../rtl/pdp8_rf.v" line 708: Ignored duplicate item in case statement. + + +"../../rtl/pdp8_rf.v" line 725: Parameter 2 is not constant in call of system task $display. + + +"../../rtl/pdp8_rf.v" line 756: Parameter 2 is not constant in call of system task $display. + + +"../../rtl/pdp8_rf.v" line 862: Parameter 2 is not constant in call of system task $display. + + +"../../rtl/pdp8_rf.v" line 868: Parameter 2 is not constant in call of system task $display. + + +"../../rtl/pdp8_rf.v" line 901: Parameter 2 is not constant in call of system task $display. + + +"../../rtl/pdp8_rf.v" line 904: Parameter 2 is not constant in call of system task $display. + + +Contents of register <is_write> in unit <pdp8_rf> never changes during circuit operation. The register is replaced by logic. + + +Contents of register <PEF> in unit <pdp8_rf> never changes during circuit operation. The register is replaced by logic. + + +Contents of register <NXD> in unit <pdp8_rf> never changes during circuit operation. The register is replaced by logic. + + +Contents of register <WLS> in unit <pdp8_rf> never changes during circuit operation. The register is replaced by logic. + + +Signal <fetch> is assigned but never used. + + +Signal <execute> is assigned but never used. + + +Signal <deferred> is assigned but never used. + + +Input <mb<11:3>> is never used. + + +Input <clk> is never used. + + +Signal <tx_over_run> is assigned but never used. + + +Signal <rx_in> is used but never assigned. Tied to value 0. + + +Signal <tx_out> is assigned but never used. + + +Signal <rx_frame_err> is assigned but never used. + + +Signal <rx_over_run> is assigned but never used. + + +Input <reset> is never used. + + +HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + + diff --git a/xilinx/pdp8/pdp8.ise b/xilinx/pdp8/pdp8.ise new file mode 100644 index 0000000..d4abb30 Binary files /dev/null and b/xilinx/pdp8/pdp8.ise differ diff --git a/xilinx/pdp8/pdp8.ise_ISE_Backup b/xilinx/pdp8/pdp8.ise_ISE_Backup new file mode 100644 index 0000000..40669ac Binary files /dev/null and b/xilinx/pdp8/pdp8.ise_ISE_Backup differ diff --git a/xilinx/pdp8/pdp8.ntrc_log b/xilinx/pdp8/pdp8.ntrc_log new file mode 100644 index 0000000..029f0b6 --- /dev/null +++ b/xilinx/pdp8/pdp8.ntrc_log @@ -0,0 +1,18 @@ +-------------------- +Xst NTRC: "/top" : OUT_OF_DATE +-------------------- +Xst NTRC: "/top" : OUT_OF_DATE +-------------------- +Xst NTRC: "/top" : OUT_OF_DATE +-------------------- +Xst NTRC: "/top" : OUT_OF_DATE +-------------------- +Xst NTRC: "/top" : OUT_OF_DATE +-------------------- +Xst NTRC: "/top" : OUT_OF_DATE +-------------------- +Xst NTRC: "/top" : OUT_OF_DATE +-------------------- +Xst NTRC: "/top" : OUT_OF_DATE +-------------------- +Xst NTRC: "/top" : OUT_OF_DATE diff --git a/xilinx/pdp8/top.cmd_log b/xilinx/pdp8/top.cmd_log new file mode 100644 index 0000000..e1e1a2d --- /dev/null +++ b/xilinx/pdp8/top.cmd_log @@ -0,0 +1,11 @@ +xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr +xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr +xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr +xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr +xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr +xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr +xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr +xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr +xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr +xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr +xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr diff --git a/xilinx/pdp8/top.lso b/xilinx/pdp8/top.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/xilinx/pdp8/top.lso @@ -0,0 +1 @@ +work diff --git a/xilinx/pdp8/top.prj b/xilinx/pdp8/top.prj new file mode 100644 index 0000000..8a1dbd7 --- /dev/null +++ b/xilinx/pdp8/top.prj @@ -0,0 +1,14 @@ +verilog work "../../rtl/ide.v" +verilog work "../../rtl/uart.v" +verilog work "../../rtl/ram_256x12.v" +verilog work "../../rtl/ide_disk.v" +verilog work "../../rtl/brg.v" +verilog work "../../rtl/ram_32kx12.v" +verilog work "../../rtl/pdp8_tt.v" +verilog work "../../rtl/pdp8_rf.v" +verilog work "../../rtl/pdp8_kw.v" +verilog work "../../rtl/pdp8_ram.v" +verilog work "../../rtl/pdp8_io.v" +verilog work "../../rtl/pdp8.v" +verilog work "../../rtl/debounce.v" +verilog work "../../rtl/top.v" diff --git a/xilinx/pdp8/top.syr b/xilinx/pdp8/top.syr new file mode 100644 index 0000000..1627e42 --- /dev/null +++ b/xilinx/pdp8/top.syr @@ -0,0 +1,666 @@ +Release 8.2.03i - xst I.34 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to ./xst/projnav.tmp +CPU : 0.00 / 0.41 s | Elapsed : 0.00 / 0.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.41 s | Elapsed : 0.00 / 0.00 s + +--> Reading design: top.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "top.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "top" +Output Format : NGC +Target Device : xc3s1000-5-ft256 + +---- Source Options +Top Module Name : top +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : YES +Resource Sharing : YES +Multiplier Style : auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 8 +Register Duplication : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +RTL Output : Yes +Global Optimization : AllClockNets +Write Timing Constraints : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : top.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling verilog file "../../rtl/ide.v" in library work +Compiling verilog file "../../rtl/uart.v" in library work +Module compiled +Compiling verilog file "../../rtl/ram_256x12.v" in library work +Module compiled +Compiling verilog file "../../rtl/ide_disk.v" in library work +Module compiled +Compiling verilog file "../../rtl/brg.v" in library work +Module compiled +Compiling verilog file "../../rtl/ram_32kx12.v" in library work +Module compiled +Compiling verilog file "../../rtl/pdp8_tt.v" in library work +Module compiled +Compiling verilog file "../../rtl/pdp8_rf.v" in library work +Module compiled +Compiling verilog file "../../rtl/pdp8_kw.v" in library work +Module compiled +Compiling verilog file "../../rtl/pdp8_ram.v" in library work +Module compiled +Compiling verilog file "../../rtl/pdp8_io.v" in library work +Module compiled +Compiling verilog file "../../rtl/pdp8.v" in library work +Module compiled +Compiling verilog file "../../rtl/debounce.v" in library work +Module compiled +Compiling verilog file "../../rtl/top.v" in library work +Module compiled +Module compiled +No errors in compilation +Analysis of file <"top.prj"> succeeded. + + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library with parameters. + D0 = "0100" + D1 = "0101" + D2 = "0110" + D3 = "0111" + E0 = "1000" + E1 = "1001" + E2 = "1010" + E3 = "1011" + F0 = "0000" + F1 = "0001" + F2 = "0010" + F3 = "0011" + H0 = "1100" + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library with parameters. + F3 = "0011" + F2 = "0010" + F1 = "0001" + F0 = "0000" + +Analyzing hierarchy for module in library with parameters. + F3 = "0011" + F2 = "0010" + F1 = "0001" + F0 = "0000" + +Analyzing hierarchy for module in library with parameters. + CA_ADDR = "000111111101001" + CIE_bit = "000001000000" + DB_begin_xfer_write = "0111" + DB_check_xfer_read = "0100" + DB_check_xfer_write = "1000" + DB_done_xfer = "1001" + DB_done_xfer1 = "1010" + DB_done_xfer2 = "1011" + DB_done_xfer3 = "1100" + DB_idle = "0000" + DB_next_xfer_incr = "0110" + DB_next_xfer_read = "0101" + DB_read_new_page = "1101" + DB_start_xfer1 = "0001" + DB_start_xfer2 = "0010" + DB_start_xfer3 = "0011" + DB_write_old_page = "1111" + DRE_bit = "010000000000" + DRL_bit = "000000000100" + EIE_bit = "000100000000" + F0 = "0000" + F1 = "0001" + F2 = "0010" + F3 = "0011" + MEX_bit = "000000111000" + NXD_bit = "000000000010" + PCA_bit = "100000000000" + PER_bit = "000000000001" + PIE_bit = "000010000000" + WC_ADDR = "000111111101000" + WLS_bit = "001000000000" + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library with parameters. + TX_CLK_DIV = "00000000000000000000101000101100" + SYS_CLK = "10111110101111000010000000" + RX_CLK_DIV = "00000000000000000000000010100010" + BAUD = "0010010110000000" + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library with parameters. + ATA_ALTER = "01110" + ATA_CMD_READ = "0000000000100000" + ATA_CMD_WRITE = "0000000000110000" + ATA_COMMAND = "10111" + ATA_CYLHIGH = "10101" + ATA_CYLLOW = "10100" + ATA_DATA = "10000" + ATA_DEVCTRL = "01110" + ATA_DRVHEAD = "10110" + ATA_ERROR = "10001" + ATA_FEATURE = "10001" + ATA_SECCNT = "10010" + ATA_SECNUM = "10011" + ATA_STATUS = "10111" + IDE_STATUS_BSY = "00000000000000000000000000000111" + IDE_STATUS_CORR = "00000000000000000000000000000010" + IDE_STATUS_DRDY = "00000000000000000000000000000110" + IDE_STATUS_DRQ = "00000000000000000000000000000011" + IDE_STATUS_DSC = "00000000000000000000000000000100" + IDE_STATUS_DWF = "00000000000000000000000000000101" + IDE_STATUS_ERR = "00000000000000000000000000000000" + IDE_STATUS_IDX = "00000000000000000000000000000001" + init0 = "00001" + init1 = "00010" + init10 = "01011" + init11 = "01100" + init2 = "00011" + init3 = "00100" + init4 = "00101" + init5 = "00110" + init6 = "00111" + init7 = "01000" + init8 = "01001" + init9 = "01010" + last0 = "10001" + last1 = "10010" + last2 = "10011" + last3 = "10100" + read0 = "01101" + read1 = "01110" + ready = "00000" + wait0 = "10101" + wait1 = "10110" + write0 = "01111" + write1 = "10000" + +Analyzing hierarchy for module in library with parameters. + s4 = "101" + s3 = "100" + s2 = "011" + s1 = "010" + s0 = "001" + idle = "000" + +Building hierarchy successfully finished. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing top module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + F0 = 4'b0000 + F1 = 4'b0001 + F2 = 4'b0010 + F3 = 4'b0011 + D0 = 4'b0100 + D1 = 4'b0101 + D2 = 4'b0110 + D3 = 4'b0111 + E0 = 4'b1000 + E1 = 4'b1001 + E2 = 4'b1010 + E3 = 4'b1011 + H0 = 4'b1100 +WARNING:Xst:883 - "../../rtl/pdp8.v" line 763: Ignored duplicate item in case statement. +WARNING:Xst:2323 - "../../rtl/pdp8.v" line 799: Parameter 2 is not constant in call of system task $display. +"../../rtl/pdp8.v" line 799: $display : HLT! %o +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + F0 = 4'b0000 + F1 = 4'b0001 + F2 = 4'b0010 + F3 = 4'b0011 +"../../rtl/pdp8_kw.v" line 88: $display : kw8i: clocks on! +"../../rtl/pdp8_kw.v" line 92: $display : CCFF +"../../rtl/pdp8_kw.v" line 99: $display : CSCF +"../../rtl/pdp8_kw.v" line 104: $display : CCEC +"../../rtl/pdp8_kw.v" line 109: $display : CECI +"../../rtl/pdp8_kw.v" line 121: $display : kw8i: set kw_flag! + +Module is correct for synthesis. + +Analyzing module in library . + F0 = 4'b0000 + F1 = 4'b0001 + F2 = 4'b0010 + F3 = 4'b0011 +WARNING:Xst:2323 - "../../rtl/pdp8_tt.v" line 142: Parameter 2 is not constant in call of system task $display. +"../../rtl/pdp8_tt.v" line 142: $display : xxx rx_data %o +WARNING:Xst:905 - "../../rtl/pdp8_tt.v" line 118: The signals are missing in the sensitivity list of always block. +WARNING:Xst:2323 - "../../rtl/pdp8_tt.v" line 211: Parameter 2 is not constant in call of system task $display. +"../../rtl/pdp8_tt.v" line 211: $display : xxx tx_data %o +"../../rtl/pdp8_tt.v" line 222: $display : xxx set tx_int +"../../rtl/pdp8_tt.v" line 264: $display : xxx assert_tx_int +Module is correct for synthesis. + +Analyzing module in library . + SYS_CLK = 26'b10111110101111000010000000 + BAUD = 16'b0010010110000000 + RX_CLK_DIV = 32'b00000000000000000000000010100010 + TX_CLK_DIV = 32'b00000000000000000000101000101100 +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + F0 = 4'b0000 + F1 = 4'b0001 + F2 = 4'b0010 + F3 = 4'b0011 + PCA_bit = 12'b100000000000 + DRE_bit = 12'b010000000000 + WLS_bit = 12'b001000000000 + EIE_bit = 12'b000100000000 + PIE_bit = 12'b000010000000 + CIE_bit = 12'b000001000000 + MEX_bit = 12'b000000111000 + DRL_bit = 12'b000000000100 + NXD_bit = 12'b000000000010 + PER_bit = 12'b000000000001 + WC_ADDR = 15'b000111111101000 + CA_ADDR = 15'b000111111101001 + DB_idle = 4'b0000 + DB_start_xfer1 = 4'b0001 + DB_start_xfer2 = 4'b0010 + DB_start_xfer3 = 4'b0011 + DB_check_xfer_read = 4'b0100 + DB_next_xfer_read = 4'b0101 + DB_next_xfer_incr = 4'b0110 + DB_begin_xfer_write = 4'b0111 + DB_check_xfer_write = 4'b1000 + DB_done_xfer = 4'b1001 + DB_done_xfer1 = 4'b1010 + DB_done_xfer2 = 4'b1011 + DB_done_xfer3 = 4'b1100 + DB_read_new_page = 4'b1101 + DB_write_old_page = 4'b1111 +WARNING:Xst:2323 - "../../rtl/pdp8_rf.v" line 575: Parameter 2 is not constant in call of system task $display. +"../../rtl/pdp8_rf.v" line 575: $display : rf: go! disk_addr %o +WARNING:Xst:905 - "../../rtl/pdp8_rf.v" line 557: The signals are missing in the sensitivity list of always block. +"../../rtl/pdp8_rf.v" line 663: $display : rf: DCMA +"../../rtl/pdp8_rf.v" line 677: $display : rf: DCIM +WARNING:Xst:883 - "../../rtl/pdp8_rf.v" line 708: Ignored duplicate item in case statement. +WARNING:Xst:2323 - "../../rtl/pdp8_rf.v" line 725: Parameter 2 is not constant in call of system task $display. +"../../rtl/pdp8_rf.v" line 725: $display : rf: DIML %o +WARNING:Xst:2323 - "../../rtl/pdp8_rf.v" line 756: Parameter 2 is not constant in call of system task $display. +"../../rtl/pdp8_rf.v" line 756: $display : rf: set DCF (CIE %b) +WARNING:Xst:2323 - "../../rtl/pdp8_rf.v" line 862: Parameter 2 is not constant in call of system task $display. +"../../rtl/pdp8_rf.v" line 862: $display : rf: read wc %o +WARNING:Xst:2323 - "../../rtl/pdp8_rf.v" line 868: Parameter 2 is not constant in call of system task $display. +"../../rtl/pdp8_rf.v" line 868: $display : rf: read ca %o +WARNING:Xst:2323 - "../../rtl/pdp8_rf.v" line 901: Parameter 2 is not constant in call of system task $display. +"../../rtl/pdp8_rf.v" line 901: $display : rf: write wc %o +WARNING:Xst:2323 - "../../rtl/pdp8_rf.v" line 904: Parameter 2 is not constant in call of system task $display. +"../../rtl/pdp8_rf.v" line 904: $display : rf: write ca %o +"../../rtl/pdp8_rf.v" line 908: $display : rf: done +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + ready = 5'b00000 + init0 = 5'b00001 + init1 = 5'b00010 + init2 = 5'b00011 + init3 = 5'b00100 + init4 = 5'b00101 + init5 = 5'b00110 + init6 = 5'b00111 + init7 = 5'b01000 + init8 = 5'b01001 + init9 = 5'b01010 + init10 = 5'b01011 + init11 = 5'b01100 + read0 = 5'b01101 + read1 = 5'b01110 + write0 = 5'b01111 + write1 = 5'b10000 + last0 = 5'b10001 + last1 = 5'b10010 + last2 = 5'b10011 + last3 = 5'b10100 + wait0 = 5'b10101 + wait1 = 5'b10110 + ATA_ALTER = 5'b01110 + ATA_DEVCTRL = 5'b01110 + ATA_DATA = 5'b10000 + ATA_ERROR = 5'b10001 + ATA_FEATURE = 5'b10001 + ATA_SECCNT = 5'b10010 + ATA_SECNUM = 5'b10011 + ATA_CYLLOW = 5'b10100 + ATA_CYLHIGH = 5'b10101 + ATA_DRVHEAD = 5'b10110 + ATA_STATUS = 5'b10111 + ATA_COMMAND = 5'b10111 + IDE_STATUS_BSY = 32'sb00000000000000000000000000000111 + IDE_STATUS_DRDY = 32'sb00000000000000000000000000000110 + IDE_STATUS_DWF = 32'sb00000000000000000000000000000101 + IDE_STATUS_DSC = 32'sb00000000000000000000000000000100 + IDE_STATUS_DRQ = 32'sb00000000000000000000000000000011 + IDE_STATUS_CORR = 32'sb00000000000000000000000000000010 + IDE_STATUS_IDX = 32'sb00000000000000000000000000000001 + IDE_STATUS_ERR = 32'sb00000000000000000000000000000000 + ATA_CMD_READ = 16'b0000000000100000 + ATA_CMD_WRITE = 16'b0000000000110000 +"../../rtl/ide_disk.v" line 196: $display : ide_disk: XXX go! +"../../rtl/ide_disk.v" line 416: $display : ide_disk: XXX last3, done +Module is correct for synthesis. + +Analyzing module in library . + idle = 3'b000 + s0 = 3'b001 + s1 = 3'b010 + s2 = 3'b011 + s3 = 3'b100 + s4 = 3'b101 +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... +INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. +INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. +INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. +INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. + +Synthesizing Unit . + Related source file is "../../rtl/debounce.v". + Found 15-bit up counter for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 1 Counter(s). + inferred 12 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/pdp8.v". +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:646 - Signal is assigned but never used. + Found 8x8-bit ROM for signal <$AUX_15>. + Found 4x1-bit ROM for signal <$mux0005>. + Found 4-bit register for signal . + Found 12-bit register for signal . + Found 12-bit adder for signal <$add0000> created at line 475. + Found 12-bit adder carry out for signal <$addsub0000> created at line 418. + Found 12-bit adder carry out for signal <$addsub0001> created at line 418. + Found 3-bit 4-to-1 multiplexer for signal <$mux0022>. + Found 12-bit adder for signal <$share0000> created at line 558. + Found 1-bit xor2 for signal <$xor0059> created at line 345. + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 15-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 4-bit 4-to-1 multiplexer for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 ROM(s). + inferred 105 D-type flip-flop(s). + inferred 6 Adder/Subtractor(s). + inferred 7 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/pdp8_kw.v". +WARNING:Xst:647 - Input > is never used. + Found 4x1-bit ROM for signal . + Found 1-bit register for signal . + Found 12-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit up counter for signal . + Summary: + inferred 1 ROM(s). + inferred 2 Counter(s). + inferred 4 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/brg.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 13-bit up counter for signal . + Found 13-bit up counter for signal . + Summary: + inferred 2 Counter(s). + inferred 2 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/uart.v". +WARNING:Xst:647 - Input is never used. +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:646 - Signal is assigned but never used. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 5 | + | Inputs | 1 | + | Outputs | 2 | + | Clock | rx_clk (rising_edge) | + | Reset | reset (positive) | + | Reset type | asynchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 5 | + | Inputs | 1 | + | Outputs | 2 | + | Clock | tx_clk (rising_edge) | + | Reset | reset (positive) | + | Reset type | asynchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit adder for signal <$addsub0000> created at line 161. + Found 4-bit comparator greatequal for signal <$cmp_ge0000> created at line 164. + Found 4-bit comparator lessequal for signal <$cmp_le0000> created at line 164. + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 4-bit up counter for signal . + Found 4-bit up counter for signal . + Summary: + inferred 2 Finite State Machine(s). + inferred 2 Counter(s). + inferred 25 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 2 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/ram_256x12.v". +WARNING:Xst:647 - Input is never used. + Found 256x12-bit single-port distributed RAM for signal . + ----------------------------------------------------------------------- + | ram_style | Auto | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 256-word x 12-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + Summary: + inferred 1 RAM(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/ide.v". + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 6 | + | Transitions | 8 | + | Inputs | 2 | + | Outputs | 5 | + | Clock | clk (rising_edge) | + | Reset | reset (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 16-bit register for signal . + Found 16-bit tristate buffer for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 16 D-type flip-flop(s). + inferred 16 Tristate(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/ram_32kx12.v". diff --git a/xilinx/pdp8/top.xst b/xilinx/pdp8/top.xst new file mode 100644 index 0000000..483f76c --- /dev/null +++ b/xilinx/pdp8/top.xst @@ -0,0 +1,53 @@ +set -tmpdir "./xst/projnav.tmp" +set -xsthdpdir "./xst" +run +-ifn top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc3s1000-5-ft256 +-top top +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso top.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-mux_extract YES +-resource_sharing YES +-mult_style auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/xilinx/pdp8/top_summary.html b/xilinx/pdp8/top_summary.html new file mode 100644 index 0000000..d00fbc9 --- /dev/null +++ b/xilinx/pdp8/top_summary.html @@ -0,0 +1,53 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PDP8 Project Status
Project File:pdp8.iseCurrent State:Synthesized
Module Name:top
  • Errors:
 
Target Device:xc3s1000-5ft256
  • Warnings:
 
Product Version:ISE 8.2.03i
  • Updated:
Tue Apr 13 13:11:50 2010
+ 
+ + +
PDP8 Partition Summary
No partition information was found.
+ + + 
+ + + + + + + + + +
Detailed Reports
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentTue Apr 13 13:11:48 2010   
Translation Report     
Map Report     
Place and Route Report     
Static Timing Report     
Bitgen Report     
+ 
+ + + +
Secondary Reports
Report NameStatusGenerated
Xplorer Report  
+ \ No newline at end of file diff --git a/xilinx/pdp8/top_vhdl.prj b/xilinx/pdp8/top_vhdl.prj new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/pdp8/xst/dump.xst/top.prj/ntrc.scr b/xilinx/pdp8/xst/dump.xst/top.prj/ntrc.scr new file mode 100644 index 0000000..84ea261 --- /dev/null +++ b/xilinx/pdp8/xst/dump.xst/top.prj/ntrc.scr @@ -0,0 +1,3 @@ +set -xsthdpdir ./xst\ +set -checkcmdline no +run -ifn top.prj -ifmt mixed -ofn top -ofmt NGC -p xc3s1000-5-ft256 -top top -opt_mode Speed -opt_level 1 -iuc NO -lso top.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract YES -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 500 -bufg 8 -register_duplication YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 -crit Speed -power 1 -mapstyle lut -fsm_encoding Auto -t XILINX -addsub_extract yes diff --git a/xilinx/pdp8/xst/work/hdllib.ref b/xilinx/pdp8/xst/work/hdllib.ref new file mode 100644 index 0000000..fe62d4c --- /dev/null +++ b/xilinx/pdp8/xst/work/hdllib.ref @@ -0,0 +1,14 @@ +MO ide_disk NULL ../../rtl/ide_disk.v vlg10/ide__disk.bin 1271178661 +MO pdp8_io NULL ../../rtl/pdp8_io.v vlg2F/pdp8__io.bin 1271178661 +MO brg NULL ../../rtl/brg.v vlg33/brg.bin 1271178661 +MO pdp8_kw NULL ../../rtl/pdp8_kw.v vlg41/pdp8__kw.bin 1271178661 +MO pdp8_rf NULL ../../rtl/pdp8_rf.v vlg53/pdp8__rf.bin 1271178661 +MO ram_32kx12 NULL ../../rtl/ram_32kx12.v vlg7A/ram__32kx12.bin 1271178661 +MO pdp8_tt NULL ../../rtl/pdp8_tt.v vlg6B/pdp8__tt.bin 1271178661 +MO debounce NULL ../../rtl/debounce.v vlg1D/debounce.bin 1271178661 +MO top NULL ../../rtl/top.v vlg6F/top.bin 1271178661 +MO ram_256x12 NULL ../../rtl/ram_256x12.v vlg37/ram__256x12.bin 1271178661 +MO pdp8 NULL ../../rtl/pdp8.v vlg5C/pdp8.bin 1271178661 +MO ide NULL ../../rtl/ide.v vlg1A/ide.bin 1271178660 +MO pdp8_ram NULL ../../rtl/pdp8_ram.v vlg73/pdp8__ram.bin 1271178661 +MO uart NULL ../../rtl/uart.v vlg48/uart.bin 1271178661 diff --git a/xilinx/pdp8/xst/work/vlg10/ide__disk.bin b/xilinx/pdp8/xst/work/vlg10/ide__disk.bin new file mode 100644 index 0000000..da40349 Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg10/ide__disk.bin differ diff --git a/xilinx/pdp8/xst/work/vlg1A/ide.bin b/xilinx/pdp8/xst/work/vlg1A/ide.bin new file mode 100644 index 0000000..ff55f5e Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg1A/ide.bin differ diff --git a/xilinx/pdp8/xst/work/vlg1D/debounce.bin b/xilinx/pdp8/xst/work/vlg1D/debounce.bin new file mode 100644 index 0000000..6e73dcd Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg1D/debounce.bin differ diff --git a/xilinx/pdp8/xst/work/vlg2F/pdp8__io.bin b/xilinx/pdp8/xst/work/vlg2F/pdp8__io.bin new file mode 100644 index 0000000..d9ee518 Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg2F/pdp8__io.bin differ diff --git a/xilinx/pdp8/xst/work/vlg33/brg.bin b/xilinx/pdp8/xst/work/vlg33/brg.bin new file mode 100644 index 0000000..0d9c9a4 Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg33/brg.bin differ diff --git a/xilinx/pdp8/xst/work/vlg37/ram__256x12.bin b/xilinx/pdp8/xst/work/vlg37/ram__256x12.bin new file mode 100644 index 0000000..210bb5e Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg37/ram__256x12.bin differ diff --git a/xilinx/pdp8/xst/work/vlg41/pdp8__kw.bin b/xilinx/pdp8/xst/work/vlg41/pdp8__kw.bin new file mode 100644 index 0000000..c148c9f Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg41/pdp8__kw.bin differ diff --git a/xilinx/pdp8/xst/work/vlg48/uart.bin b/xilinx/pdp8/xst/work/vlg48/uart.bin new file mode 100644 index 0000000..170eef7 Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg48/uart.bin differ diff --git a/xilinx/pdp8/xst/work/vlg53/pdp8__rf.bin b/xilinx/pdp8/xst/work/vlg53/pdp8__rf.bin new file mode 100644 index 0000000..9aa2bea Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg53/pdp8__rf.bin differ diff --git a/xilinx/pdp8/xst/work/vlg5C/pdp8.bin b/xilinx/pdp8/xst/work/vlg5C/pdp8.bin new file mode 100644 index 0000000..59e4972 Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg5C/pdp8.bin differ diff --git a/xilinx/pdp8/xst/work/vlg6B/pdp8__tt.bin b/xilinx/pdp8/xst/work/vlg6B/pdp8__tt.bin new file mode 100644 index 0000000..b2698d4 Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg6B/pdp8__tt.bin differ diff --git a/xilinx/pdp8/xst/work/vlg6F/top.bin b/xilinx/pdp8/xst/work/vlg6F/top.bin new file mode 100644 index 0000000..947eefa Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg6F/top.bin differ diff --git a/xilinx/pdp8/xst/work/vlg73/pdp8__ram.bin b/xilinx/pdp8/xst/work/vlg73/pdp8__ram.bin new file mode 100644 index 0000000..b55c969 Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg73/pdp8__ram.bin differ diff --git a/xilinx/pdp8/xst/work/vlg7A/ram__32kx12.bin b/xilinx/pdp8/xst/work/vlg7A/ram__32kx12.bin new file mode 100644 index 0000000..9d3e3cc Binary files /dev/null and b/xilinx/pdp8/xst/work/vlg7A/ram__32kx12.bin differ