From 6a67dce53ababd66e1bddfa30a24d735884e4eef Mon Sep 17 00:00:00 2001 From: brad Date: Wed, 14 Apr 2010 23:41:35 +0000 Subject: [PATCH] brought rs232 to top --- rtl/ide_disk.v | 4 ++++ rtl/pdp8.v | 6 +++--- rtl/pdp8_io.v | 36 ++++++++++++++++++++++++------------ rtl/pdp8_kw.v | 12 ++++++++++++ rtl/pdp8_ram.v | 2 -- rtl/pdp8_rf.v | 37 ++++++++++++++++++++++++++++++------- rtl/pdp8_tt.v | 29 +++++++++++++++++++---------- rtl/top.v | 8 +++++--- rtl/uart.v | 14 +++++++------- 9 files changed, 104 insertions(+), 44 deletions(-) diff --git a/rtl/ide_disk.v b/rtl/ide_disk.v index 96234ef..42b9fa0 100644 --- a/rtl/ide_disk.v +++ b/rtl/ide_disk.v @@ -193,7 +193,9 @@ module ide_disk(clk, reset, begin ide_state_next = init0; clear_done = 1; +`ifdef debug $display("ide_disk: XXX go!"); +`endif end end @@ -413,7 +415,9 @@ module ide_disk(clk, reset, begin clear_done = 1; ide_state_next = ready; +`ifdef debug $display("ide_disk: XXX last3, done"); +`endif end default: diff --git a/rtl/pdp8.v b/rtl/pdp8.v index 1664db3..b106e5d 100644 --- a/rtl/pdp8.v +++ b/rtl/pdp8.v @@ -758,9 +758,7 @@ module pdp8(clk, reset, mq <= ac; ac <= 0; end - 3'b100: ac <= ac | mq; - //3'b101: tmq <= mq; - 3'b100: ac <= mq; /* MQA */ + 3'b100: ac <= ac | mq; /* MQA */ 3'b101: ac <= mq; endcase end @@ -796,7 +794,9 @@ module pdp8(clk, reset, ac <= ac | switches; if (mb[1]) begin +`ifdef debug $display("HLT! %o", mb); +`endif run <= 0; end end diff --git a/rtl/pdp8_io.v b/rtl/pdp8_io.v index 7bb44a7..1390f0a 100644 --- a/rtl/pdp8_io.v +++ b/rtl/pdp8_io.v @@ -3,14 +3,18 @@ // Dev 2006 Brad Parker brad@heeltoe.com // Revamp 2009 Brad Parker brad@heeltoe.com -module pdp8_io(clk, reset, iot, state, mb, +module pdp8_io(clk, brgclk, reset, iot, state, mb, io_data_in, io_data_out, io_select, io_data_avail, io_interrupt, io_skip, io_clear_ac, io_ram_read_req, io_ram_write_req, io_ram_done, io_ram_ma, io_ram_in, io_ram_out, - ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus); + ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus, + rs232_in, rs232_out); - input clk, reset, iot; + input clk; + input brgclk; + input reset; + input iot; input [11:0] io_data_in; input [11:0] mb; input [3:0] state; @@ -29,6 +33,15 @@ module pdp8_io(clk, reset, iot, state, mb, output wire [14:0] io_ram_ma; output wire [11:0] io_ram_out; + output ide_dior; + output ide_diow; + output [1:0] ide_cs; + output [2:0] ide_da; + inout [15:0] ide_data_bus; + + input rs232_in; + output rs232_out; + wire kw_io_selected; wire kw_io_interrupt; wire kw_io_skip; @@ -47,13 +60,6 @@ module pdp8_io(clk, reset, iot, state, mb, wire rf_io_skip; wire rf_io_clear_ac; - output ide_dior; - output ide_diow; - output [1:0] ide_cs; - output [2:0] ide_da; - inout [15:0] ide_data_bus; - - pdp8_kw kw(.clk(clk), .reset(reset), .iot(iot), @@ -66,7 +72,7 @@ module pdp8_io(clk, reset, iot, state, mb, .io_skip(kw_io_skip)); pdp8_tt tt(.clk(clk), - .brgclk(/*brgclk*/clk), + .brgclk(brgclk), .reset(reset), .iot(iot), .state(state), @@ -78,7 +84,10 @@ module pdp8_io(clk, reset, iot, state, mb, .io_data_out(tt_io_data_out), .io_data_avail(tt_io_data_avail), .io_interrupt(tt_io_interrupt), - .io_skip(tt_io_skip)); + .io_skip(tt_io_skip), + + .uart_in(rs232_in), + .uart_out(rs232_out)); pdp8_rf tf(.clk(clk), .reset(reset), @@ -107,6 +116,9 @@ module pdp8_io(clk, reset, iot, state, mb, .ide_da(ide_da), .ide_data_bus(ide_data_bus)); + assign tt_io_clear_ac = 1'b0; + assign rf_io_clear_ac = 1'b0; + assign io_data_out = tt_io_selected ? tt_io_data_out : rf_io_selected ? rf_io_data_out : diff --git a/rtl/pdp8_kw.v b/rtl/pdp8_kw.v index cad917b..98629f8 100644 --- a/rtl/pdp8_kw.v +++ b/rtl/pdp8_kw.v @@ -85,28 +85,38 @@ module pdp8_kw(clk, reset, iot, state, mb, begin kw_int_en <= 1'b1; kw_clk_en <= 1'b1; +`ifdef debug $display("kw8i: clocks on!"); +`endif end 3'o2: begin +`ifdef debug $display("CCFF"); +`endif kw_flag <= 1'b0; kw_clk_en <= 1'b0; kw_int_en <= 1'b0; end 3'o3: begin +`ifdef debug $display("CSCF"); +`endif kw_flag <= 1'b0; end 3'o6: begin +`ifdef debug $display("CCEC"); +`endif kw_clk_en <= 1; end 3'o7: begin +`ifdef debug $display("CECI"); +`endif kw_clk_en <= 1; kw_int_en <= 1; end @@ -118,7 +128,9 @@ module pdp8_kw(clk, reset, iot, state, mb, if (assert_kw_flag) begin kw_flag <= 1; +`ifdef debug if (kw_flag == 0) $display("kw8i: set kw_flag!\n"); +`endif end end diff --git a/rtl/pdp8_ram.v b/rtl/pdp8_ram.v index 766668c..d634d92 100644 --- a/rtl/pdp8_ram.v +++ b/rtl/pdp8_ram.v @@ -35,8 +35,6 @@ module pdp8_ram(clk, reset, addr, data_in, data_out, rd, wr, .CE_N(1'b0), .WE_N(~wr)); `else - wire [15:0] ram1_io; - // wire sram1_ub, sram1_lb; diff --git a/rtl/pdp8_rf.v b/rtl/pdp8_rf.v index cd82a91..043e36e 100644 --- a/rtl/pdp8_rf.v +++ b/rtl/pdp8_rf.v @@ -1,6 +1,8 @@ // RF08 Emulation using IDE disk // brad@heeltoe.com +//`define debug_rf + /* RF08 Sizes: @@ -523,7 +525,7 @@ module pdp8_rf(clk, reset, iot, state, mb, assign buff_addr = ide_active ? ide_buffer_addr : buffer_addr; assign buff_in = ide_active ? ide_buffer_out : buffer_hold; - assign buff_rd = ide_active ? ide_buffer_rd : 1'b1; + assign buff_rd = ide_active ? ide_buffer_rd : 1'b1/*buffer_rd?*/; assign buff_wr = ide_active ? ide_buffer_wr : buffer_wr; // ide disk @@ -552,8 +554,10 @@ module pdp8_rf(clk, reset, iot, state, mb, // // combinatorial logic - always @(state or - ADC or DRL or PER or WLS or NXD or DCF) + always @(state or iot or io_select or mb or io_data_in or + ADC or DRL or PER or WLS or NXD or DCF or + PCA or DRE or EIE or PIE or CIE or MEX or DMA or EMA or + disk_addr) begin // sampled during f1 io_skip = 0; @@ -572,7 +576,9 @@ module pdp8_rf(clk, reset, iot, state, mb, begin io_data_out = 0; dma_start = 1'b1; +`ifdef debug $display("rf: go! disk_addr %o", disk_addr); +`endif end 3'o5: // DMAW begin @@ -660,7 +666,9 @@ module pdp8_rf(clk, reset, iot, state, mb, 6'o60: // DCMA if (mb[2:0] == 3'b001) begin -$display("rf: DCMA"); +`ifdef debug + $display("rf: DCMA"); +`endif DMA <= 0; PEF <= 1'b0; NXD <= 1'b0; @@ -674,7 +682,9 @@ $display("rf: DCMA"); PIE <= 1'b0; CIE <= 1'b0; MEX <= 3'b0; -$display("rf: DCIM"); +`ifdef debug + $display("rf: DCIM"); +`endif end 3'o2: // DSAC begin @@ -724,7 +734,9 @@ is_read <= 1'b1; PIE <= io_data_in[7]; CIE <= io_data_in[6]; MEX <= io_data_in[5:3]; -$display("rf: DIML %o", io_data_in); +`ifdef debug + $display("rf: DIML %o", io_data_in); +`endif end endcase // case(mb[2:0]) @@ -755,7 +767,9 @@ $display("rf: DIML %o", io_data_in); DMA <= disk_addr[11:0]; is_read <= 1'b0; is_write <= 1'b0; -$display("rf: set DCF (CIE %b)", CIE); +`ifdef debug + $display("rf: set DCF (CIE %b)", CIE); +`endif DCF <= 1'b1; end @@ -861,13 +875,18 @@ $display("rf: set DCF (CIE %b)", CIE); begin dma_wc <= ram_in + 12'o0001; db_done <= 0; +`ifdef debug if (ram_done) $display("rf: read wc %o", ram_in); +`endif end DB_start_xfer2: begin dma_addr <= { MEX, ram_in + 12'o0001 }; +`ifdef debug + if (ram_done) $display("rf: read ca %o", ram_in); +`endif end DB_start_xfer3: @@ -899,15 +918,19 @@ $display("rf: set DCF (CIE %b)", CIE); DB_check_xfer_write: buffer_dirty <= 1; +`ifdef debug DB_done_xfer: if (ram_done) $display("rf: write wc %o", dma_wc); DB_done_xfer1: if (ram_done) $display("rf: write ca %o", dma_addr); +`endif DB_done_xfer2: begin +`ifdef debug $display("rf: done"); +`endif db_done <= 1; end diff --git a/rtl/pdp8_tt.v b/rtl/pdp8_tt.v index b36f1fb..af0ec22 100644 --- a/rtl/pdp8_tt.v +++ b/rtl/pdp8_tt.v @@ -1,17 +1,20 @@ // PDP8 console emulation // brad@heeltoe.com -//`define sim_time - +`ifdef debug `define debug_tt_int 1 //`define debug_tt_reg 1 //`define debug_tt_state 1 `define debug_tt_data 1 +`endif + +//`define sim_time module pdp8_tt(clk, brgclk, reset, iot, state, mb, io_data_in, io_data_out, io_select, io_selected, - io_data_avail, io_interrupt, io_skip); + io_data_avail, io_interrupt, io_skip, + uart_in, uart_out); input clk; input brgclk; @@ -22,15 +25,17 @@ module pdp8_tt(clk, brgclk, reset, input [11:0] mb; input [11:0] io_data_in; input [5:0] io_select; + input uart_in; output reg [11:0] io_data_out; output reg io_selected; output io_data_avail; output io_interrupt; output reg io_skip; + output uart_out; // internal state - reg [11:0] tx_data; + reg [7:0] tx_data; reg tx_int; wire tx_empty; wire tx_ack; @@ -80,7 +85,7 @@ module pdp8_tt(clk, brgclk, reset, .tx_clk(uart_tx_clk), .tx_req(tto_req), .tx_ack(tx_ack), - .tx_data(tx_data[7:0]), + .tx_data(tx_data), .tx_empty(tx_empty), .rx_clk(uart_rx_clk), @@ -96,14 +101,17 @@ module pdp8_tt(clk, brgclk, reset, .tx_clk(uart_tx_clk), .tx_req(tto_req), .tx_ack(tx_ack), - .tx_data(tx_data[7:0]), + .tx_data(tx_data), .tx_empty(tx_empty), .rx_clk(uart_rx_clk), .rx_req(tti_req), .rx_ack(rx_ack), .rx_data(rx_data[7:0]), - .rx_empty(rx_empty)); + .rx_empty(rx_empty), + + .rx_in(uart_in), + .tx_out(uart_out)); `endif // interrupt output @@ -114,7 +122,8 @@ module pdp8_tt(clk, brgclk, reset, assign rx_data[11:8] = 4'b0; // combinatorial - always @(state or rx_int or tx_int) + always @(state or iot or io_select or mb or + rx_int or tx_int or io_data_in or rx_data) begin // sampled during f1 io_skip = 1'b0; @@ -171,7 +180,7 @@ module pdp8_tt(clk, brgclk, reset, rx_int <= 0; tx_int <= 0; - tx_data <= 0; + tx_data <= 8'b0; end else begin @@ -206,7 +215,7 @@ module pdp8_tt(clk, brgclk, reset, end if (mb[2]) begin - tx_data <= io_data_in; + tx_data <= io_data_in[7:0]; `ifdef debug_tt_data $display("xxx tx_data %o", io_data_in); `endif diff --git a/rtl/top.v b/rtl/top.v index 4240bf0..f90f310 100644 --- a/rtl/top.v +++ b/rtl/top.v @@ -14,8 +14,8 @@ module top(rs232_txd, rs232_rxd, sram2_io, sram2_ce_n, sram2_ub_n, sram2_lb_n, ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da); - output rs232_txd; input rs232_rxd; + output rs232_txd; input [3:0] button; @@ -96,7 +96,6 @@ module top(rs232_txd, rs232_rxd, wire [14:0] ram_addr; wire [11:0] io_data_in; wire [11:0] io_data_out; - wire [11:0] io_addr; wire io_data_avail; wire io_interrupt; wire io_skip; @@ -147,6 +146,7 @@ module top(rs232_txd, rs232_rxd, .ext_ram_out(ext_ram_in)); pdp8_io io(.clk(clk), + .brgclk(clk), .reset(reset), .iot(iot), .state(state), @@ -168,7 +168,9 @@ module top(rs232_txd, rs232_rxd, .ide_diow(ide_diow), .ide_cs(ide_cs), .ide_da(ide_da), - .ide_data_bus(ide_data_bus)); + .ide_data_bus(ide_data_bus), + .rs232_in(rs232_rxd), + .rs232_out(rs232_txd)); pdp8_ram ram(.clk(clk), .reset(reset), diff --git a/rtl/uart.v b/rtl/uart.v index a22e0fc..063f363 100644 --- a/rtl/uart.v +++ b/rtl/uart.v @@ -4,8 +4,8 @@ module uart(clk, reset, tx_clk, tx_req, tx_ack, tx_data, tx_empty, - rx_clk, rx_req, rx_ack, rx_data, rx_empty/*,*/ - /*rx_in, tx_out*/); + rx_clk, rx_req, rx_ack, rx_data, rx_empty, + rx_in, tx_out); input clk; input reset; @@ -13,18 +13,18 @@ module uart(clk, reset, input tx_req; output tx_ack; input [7:0] tx_data; -// input tx_enable; -// output tx_out; + output tx_out; output tx_empty; input rx_clk; input rx_req; output rx_ack; output [7:0] rx_data; -// input rx_enable; -// input rx_in; -wire rx_in; + input rx_in; output rx_empty; +// input tx_enable; +// input rx_enable; + reg tx_ack; reg rx_ack;