From 8a2da8d77843de33fc353d4349eaae6b4d5df2d0 Mon Sep 17 00:00:00 2001 From: brad Date: Sun, 11 Apr 2010 10:30:37 +0000 Subject: [PATCH] debugging --- rtl/ide_disk.v | 52 ++++++++++++------- rtl/pdp8_rf.v | 127 ++++++++++++++++++++++++++++++++++------------- rtl/ram_256x12.v | 6 +-- 3 files changed, 130 insertions(+), 55 deletions(-) diff --git a/rtl/ide_disk.v b/rtl/ide_disk.v index 0285de8..c6493ab 100644 --- a/rtl/ide_disk.v +++ b/rtl/ide_disk.v @@ -7,22 +7,23 @@ module ide_disk(clk, reset, ide_lba, ide_read_req, ide_write_req, ide_error, ide_done, buffer_addr, buffer_rd, buffer_wr, - buffer_in, buffer_out); + buffer_in, buffer_out, + ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da); input clk; input reset; - input [24:0] ide_lba; + input [23:0] ide_lba; input ide_read_req; input ide_write_req; output ide_error; output ide_done; - output [7:0] buffer_addr; - output buffer_rd; - output buffer_wr; + output reg [7:0] buffer_addr; + output reg buffer_rd; + output reg buffer_wr; + output reg [11:0] buffer_out; output [11:0] buffer_in; - output [11:0] buffer_out; parameter [4:0] ready = 5'd0, @@ -87,8 +88,18 @@ module ide_disk(clk, reset, output [1:0] ide_cs; output [2:0] ide_da; + // + reg [4:0] ide_state; + reg [4:0] ide_state_next; + reg [7:0] offset; reg [7:0] wc; + reg err; + reg done; + + reg set_done, clear_done; + reg set_err, clear_err; + reg inc_offset; // ide ide1(.clk(clk), .reset(reset), @@ -99,16 +110,20 @@ module ide_disk(clk, reset, .ide_cs(ide_cs), .ide_da(ide_da)); // - wire [23:0] lba = ide_lba; - wire start = ide_read_req | ide_write_req; + wire [23:0] lba; + wire start; + assign lba = ide_lba; + assign start = ide_read_req | ide_write_req; + assign ide_done = done; + // - alway @(posedge clk) + always @(posedge clk) if (reset) begin err <= 1'b0; - done <= 1'b1; + done <= 1'b0; offset <= 0; wc <= 0; end @@ -142,6 +157,8 @@ module ide_disk(clk, reset, else begin ide_state <= ide_state_next; + //if (ide_state_next != ready) + //$display("ide_state %d", ide_state_next); end always @(ide_state or lba or start or @@ -150,8 +167,6 @@ module ide_disk(clk, reset, begin ide_state_next = ide_state; - assert_int = 0; - set_err = 0; clear_err = 0; @@ -176,13 +191,13 @@ module ide_disk(clk, reset, if (start) begin ide_state_next = init0; + clear_done = 1; $display("ide_disk: XXX go!"); end end init0: begin - clear_done = 1; ata_addr = ATA_STATUS; ata_rd = 1; if (ata_done && @@ -335,15 +350,15 @@ module ide_disk(clk, reset, begin //buffer write buffer_addr = offset; - buffer_out = ata_out; + buffer_out = ata_out[11:0]; if (0) $display("read1: XXX ata_out %o, buffer_addr %o", ata_out, buffer_addr); buffer_wr = 1; - inc_offset = 1; +// inc_offset = 1; - if (wc == 16'h0000) + if (wc == 8'hff) ide_state_next = last0; else // if (wc == 16'hff00) @@ -358,14 +373,14 @@ module ide_disk(clk, reset, buffer_addr = offset; buffer_rd = 1; - ata_in = dma_data_in; + ata_in = {4'b0, buffer_in}; inc_offset = 1; ide_state_next = write1; end write1: begin - if (wc == 0) + if (wc == 9'hff) ide_state_next = last0; else // if (wc == 16'hff00) @@ -399,6 +414,7 @@ module ide_disk(clk, reset, last3: begin + clear_done = 1; ide_state_next = ready; $display("ide_disk: XXX last3, done"); end diff --git a/rtl/pdp8_rf.v b/rtl/pdp8_rf.v index 386dac0..9a28866 100644 --- a/rtl/pdp8_rf.v +++ b/rtl/pdp8_rf.v @@ -1,6 +1,8 @@ /* - RF08 + RF08 Emulation using IDE disk + RF08 Sizes: + 2048 words/track 11 bits 128 tracks 7 bits 4 disks 2 bits @@ -12,7 +14,7 @@ ddtttttttwwwwwwwwwww ema 876543210 - mapped to IDE drive; + mapping RF08 to IDE disk drive 2048 x 12 bits -> 2048 x 16 bits = 8 blocks of 512 bytes each track is 8 blocks each disk is (128 * 8) = 1024 blocks @@ -23,18 +25,18 @@ ema bits 7 & 8 select which rs08 disk ema bits 6 - 0 select disk head (track #) - dma contains lower disk word address + dma contains lower disk word address (offset into block) - writes to dma trigger; adc is asserted after match w/disk + writes to dma trigger i/o; adc is asserted after match w/disk ------------- - memory: + PDP-8 memory: 7750 word count 7751 current address - iot: + PDP-8 IOT's: 660x 661x @@ -87,15 +89,16 @@ 6646 DMMT Maintenance - uses 3 cycle data break + Real RF08 uses 3 cycle data break - ac 8:0, ac 10:0 => 20 bit {EMA,DMA} - 20 bit {EMA,DMA} = { disk-select, track-select 6:0, word-select 11:0 } + ac 8:0, ac 10:0 => 20 bit {EMA,DMA} + 20 bit {EMA,DMA} = { disk-select, track-select 6:0, word-select 11:0 } status + EIE = WLS | DRL | NXD | PER + */ -// EIE = WLS | DRL | NXD | PER /* 3 cycle data break @@ -127,6 +130,9 @@ requested when the data transfer is completed and the service routine will process the information. ----------- ----------- ----------- ----------- +*/ + +/* HIGH LEVEL DISK STATE MACHINE: @@ -358,7 +364,8 @@ module pdp8_rf(clk, reset, iot, state, mb, io_data_in, io_data_out, io_select, io_selected, io_data_avail, io_interrupt, io_skip, ram_read_req, ram_write_req, ram_done, - ram_ma, ram_in, ram_out); + ram_ma, ram_in, ram_out, + ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus); input clk, reset, iot; input [11:0] io_data_in; @@ -379,6 +386,14 @@ module pdp8_rf(clk, reset, iot, state, mb, output [11:0] ram_out; output [14:0] ram_ma; + output ide_dior; + output ide_diow; + output [1:0] ide_cs; + output [2:0] ide_da; + inout [15:0] ide_data_bus; + + // ------------------------------------------------------- + parameter [3:0] F0 = 4'b0000, F1 = 4'b0001, @@ -463,7 +478,8 @@ module pdp8_rf(clk, reset, iot, state, mb, wire ide_read_req; wire ide_write_req; wire ide_done; - + wire ide_error; + // assign io_interrupt = (CIE & db_done) || (PIE & PCA) || @@ -474,16 +490,62 @@ module pdp8_rf(clk, reset, iot, state, mb, assign buffer_matches_DMA = buffer_disk_addr[19:8] == disk_addr[19:8]; assign buffer_addr = disk_addr[7:0]; - assign ide_done = 1; + // + // sector buffer + // + wire ide_active; + wire [7:0] buff_addr; + wire [11:0] buff_in; + wire [11:0] buff_out; + wire buff_rd; + wire buff_wr; + wire [7:0] ide_buffer_addr; + wire [23:0] ide_block_number; + wire [11:0] ide_buffer_in; + wire [11:0] ide_buffer_out; + // ide sector buffer - ram_256x12 buffer(.A(buffer_addr), - .DI(buffer_hold), - .DO(buffer_out), - .CE_N(1'b0), - .WE_N(~buffer_wr)); + ram_256x12 buffer(.A(buff_addr), + .DI(buff_in), + .DO(buff_out), + .CE_N(~buff_rd), + .WE_N(~buff_wr)); + + assign ide_active = ide_read_req | ide_write_req; - // combinatorial + assign buff_addr = ide_active ? ide_buffer_addr : buffer_addr; + assign buff_in = ide_active ? ide_buffer_out : buffer_hold; + assign buff_out = ide_active ? ide_buffer_in : buffer_out; + assign buff_rd = ide_active ? ide_buffer_rd : 1'b1; + assign buff_wr = ide_active ? ide_buffer_wr : buffer_wr; + + // ide disk + ide_disk disk(.clk(clk), + .reset(reset), + .ide_lba(ide_block_number), + .ide_read_req(ide_read_req), + .ide_write_req(ide_write_req), + .ide_error(ide_error), + .ide_done(ide_done), + .buffer_addr(ide_buffer_addr), + .buffer_rd(ide_buffer_rd), + .buffer_wr(ide_buffer_wr), + .buffer_in(ide_buffer_in), + .buffer_out(ide_buffer_out), + .ide_data_bus(ide_data_bus), + .ide_dior(ide_dior), + .ide_diow(ide_diow), + .ide_cs(ide_cs), + .ide_da(ide_da)); + + assign ide_block_number = { 12'b0, disk_addr[19:8] }; + + // + // RF controller + // + + // combinatorial logic always @(state or ADC or DRL or PER or WLS or NXD or DCF) begin @@ -499,7 +561,7 @@ module pdp8_rf(clk, reset, iot, state, mb, 6'o60: begin io_selected = 1'b1; - case (mb[2:0]) + case (mb[2:0] ) 3'o3: // DMAR begin io_data_out = 0; @@ -653,14 +715,9 @@ module pdp8_rf(clk, reset, iot, state, mb, end // if (iot) -// F2: -// begin -// if (io_interrupt) -// $display("iot2 %t, reset io_interrupt", $time); -// -// // sampled during f0 -// io_interrupt <= 0; -// end + F2: + begin + end // F3 is a convenient time to do this // note that state machine waits when done till next F2 @@ -676,7 +733,7 @@ module pdp8_rf(clk, reset, iot, state, mb, endcase // case(state) - // comb logic for next state + // comb logic to create 'next state' always @(*) begin db_next_state = DB_idle; @@ -734,6 +791,7 @@ module pdp8_rf(clk, reset, iot, state, mb, db_next_state = ide_done ? (is_read ? DB_check_xfer_read:DB_check_xfer_write) : DB_read_new_page; + DB_write_old_page: db_next_state = ide_done ? DB_read_new_page : DB_write_old_page; @@ -816,12 +874,11 @@ module pdp8_rf(clk, reset, iot, state, mb, buffer_dirty <= 0; buffer_disk_addr[19:8] <= disk_addr[19:8]; end - - endcase // case (db_state) - end // else: !if(reset) + endcase + end // - // external ram control + // external ram control (for dma to/from pdp-8 memory) // assign ram_ma = db_state == DB_start_xfer1 ? WC_ADDR : @@ -853,13 +910,14 @@ module pdp8_rf(clk, reset, iot, state, mb, assign buffer_wr = db_state == DB_check_xfer_write && buffer_matches_DMA; assign ide_read_req = db_state == DB_read_new_page; - assign ide_write = db_state == DB_write_old_page; + assign ide_write_req = db_state == DB_write_old_page; // // RF08 state // assign ADC = buffer_matches_DMA; + // fake the photocell sensor always @(posedge clk) if (reset) photocell_counter <= 0; @@ -870,6 +928,7 @@ module pdp8_rf(clk, reset, iot, state, mb, assign DRE = PCA; assign DCF = db_done; + /* we don't support write lock */ always @(posedge clk) if (reset) begin diff --git a/rtl/ram_256x12.v b/rtl/ram_256x12.v index e6786ae..f1fcded 100644 --- a/rtl/ram_256x12.v +++ b/rtl/ram_256x12.v @@ -1,9 +1,9 @@ /* 256x12 static ram */ module ram_256x12(A, DI, DO, CE_N, WE_N); - input[14:0] A; - input [11:0] DI; - input CE_N, WE_N; + input [7:0] A; + input [11:0] DI; + input CE_N, WE_N; output [11:0] DO; reg [11:0] ram [0:255];