diff --git a/verif/ram_s3board.v b/verif/ram_s3board.v
index 531ac11..2505665 100644
--- a/verif/ram_s3board.v
+++ b/verif/ram_s3board.v
@@ -82,24 +82,28 @@ module ram_s3board(ram_a, ram_oe_n, ram_we_n,
 	     ram1.ram_l[i] = 7'b0;
 	  end
 
-`ifdef __ICARUS__
- `define no_scan
-`endif
 `ifdef verilator
  `define no_scan
 `endif
 
+`ifdef __ICARUS__
+       n = $value$plusargs("test=%s", testfilename);
+`endif
+       
+`ifdef __CVER__
+       n = $scan$plusargs("test=", testfilename);
+`endif
+
+
 `ifdef no_scan
 	n = 0;
-`else
- 	n = $scan$plusargs("test=", testfilename);
 `endif
 	if (n > 0)
 	  begin
 	     $display("ram_s3board: code filename: %s", testfilename);
 	     file = $fopen(testfilename, "r");
 
-	     while ($fscanf(file, "%o %o", i, v) > 0)
+	     while ($fscanf(file, "%o %o\n", i, v) > 0)
 	       begin
 		  //$display("ram_s3board[%0o] <- %o", i, v);
 		  ram1.ram_h[i] = v[15:8];
diff --git a/verif/run.sh b/verif/run.sh
index ebfe991..e895203 100755
--- a/verif/run.sh
+++ b/verif/run.sh
@@ -4,5 +4,7 @@ cver +showpc +cycles=500000 +test=tss8_init.mem +pc=24200 +loadvpi=../pli/ide/pl
 
 #cver +showpc +test=../tests/diags/MAINDEC-08-D5EB.mem +pc=0200 +switches=4000 +cycles=50000 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v >zz
 
+#cver +cycles=1000000 +test=boot.mem +pc=7750 +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap test_pdp8.v >yy2
+
 #grep "rf: go\!" xx
-#cat xx | ../utils/ushow/ushow 
\ No newline at end of file
+#cat xx | ../utils/ushow/ushow 
diff --git a/verif/test_io.v b/verif/test_io.v
index cc59590..330ca97 100644
--- a/verif/test_io.v
+++ b/verif/test_io.v
@@ -2,8 +2,12 @@
 // testing top end for pdp8_io.v
 //
 
+`define debug
+`define sim_time
+
 `include "../rtl/pdp8_tt.v"
 `include "../rtl/pdp8_rf.v"
+`include "../rtl/pdp8_kw.v"
 `include "../rtl/pdp8_io.v"
 
 `include "../verif/fake_uart.v"
@@ -44,7 +48,11 @@ module test;
    wire [1:0]  ide_cs;
    wire [2:0]  ide_da;
 
+   reg 	       rs232_in;
+   wire        rs232_out;
+   
    pdp8_io io(.clk(clk),
+	      .brgclk(clk),
 	      .reset(reset),
 	      .iot(iot),
 	      .state(state),
@@ -66,7 +74,9 @@ module test;
 	      .ide_diow(ide_diow),
 	      .ide_cs(ide_cs),
 	      .ide_da(ide_da),
-	      .ide_data_bus(ide_data_bus));
+	      .ide_data_bus(ide_data_bus),
+	      .rs232_in(rs232_in),
+	      .rs232_out(rs232_out));
 
   initial
     begin
@@ -76,38 +86,39 @@ module test;
       $dumpvars(0, test.io);
     end
 
-  initial
-    begin
-      clk = 0;
-      reset = 0;
+   initial
+     begin
+	clk = 0;
+	reset = 0;
+	rs232_in = 0;
+	
+	#1 begin
+           reset = 1;
+	end
 
-    #1 begin
-         reset = 1;
-       end
+	#50 begin
+           reset = 0;
+	end
+	
+	#3000 $finish;
+     end
 
-    #50 begin
-         reset = 0;
-       end
-  
-      #3000 $finish;
-    end
+   always
+     begin
+	#10 clk = 0;
+	#10 clk = 1;
+     end
 
-  always
-    begin
-      #10 clk = 0;
-      #10 clk = 1;
-    end
+   //----
+   integer cycle;
 
-  //----
-  integer cycle;
+   initial
+     cycle = 0;
 
-  initial
-    cycle = 0;
-
-  always @(posedge io.clk)
-    begin
-      cycle = cycle + 1;
-    end
+   always @(posedge io.clk)
+     begin
+	cycle = cycle + 1;
+     end
 
 endmodule
 
diff --git a/verif/test_pdp8.v b/verif/test_pdp8.v
index f86e998..eadb0c6 100644
--- a/verif/test_pdp8.v
+++ b/verif/test_pdp8.v
@@ -2,9 +2,17 @@
 // test bench top end for pdp8.v
 //
 
+`ifdef __ICARUS__
+ `define sim
+`endif
+
 `ifdef __CVER__
-`define debug
-`define sim_time
+ `define sim
+`endif
+
+`ifdef sim
+ `define debug
+ `define sim_time
 //`define debug_s3ram
 `endif
 
@@ -78,6 +86,9 @@ module test;
    wire [1:0]  ide_cs;
    wire [2:0]  ide_da;
 
+   reg        rs232_in;
+   wire        rs232_out;
+   
   pdp8 cpu(.clk(clk),
 	   .reset(reset),
 	   .ram_addr(ram_addr),
@@ -104,6 +115,7 @@ module test;
 	   .ext_ram_out(ext_ram_in));
    
    pdp8_io io(.clk(clk),
+	      .brgclk(clk),
 	      .reset(reset),
 	      .iot(iot),
 	      .state(state),
@@ -125,7 +137,9 @@ module test;
 	      .ide_diow(ide_diow),
 	      .ide_cs(ide_cs),
 	      .ide_da(ide_da),
-	      .ide_data_bus(ide_data_bus));
+	      .ide_data_bus(ide_data_bus),
+	      .rs232_in(rs232_in),
+	      .rs232_out(rs232_out));
 
    pdp8_ram ram(.clk(clk),
 		.reset(reset), 
@@ -172,8 +186,9 @@ module test;
        clk = 0;
        reset = 0;
        switches = 0;
-       max_cycles = 0;
+       rs232_in = 0;
 
+       max_cycles = 0;
        max_cycles = 100;
        starting_pc = 15'o00200;