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41 lines
612 B
Verilog
41 lines
612 B
Verilog
// debounce.v
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module debounce(clk, in, out);
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input clk;
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input in;
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output out;
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`ifdef sim_time
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reg [1:0] clkdiv;
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`else
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reg [14:0] clkdiv;
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`endif
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reg slowclk;
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reg [9:0] hold;
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reg onetime;
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initial
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begin
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onetime = 0;
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hold = 0;
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clkdiv = 0;
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slowclk = 0;
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end
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assign out = hold == 10'b1111111111 || ~onetime;
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always @(posedge clk)
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begin
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clkdiv <= clkdiv + 15'b1;
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if (clkdiv == 0)
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slowclk <= ~slowclk;
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end
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always @(posedge slowclk)
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begin
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hold <= { hold[8:0], in };
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onetime <= 1;
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end
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endmodule
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