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Josh Dersch 9dce55ea3a Many tiny fixes. TSS/8 now runs from RK05! Long delay on program exit; suspect hung device.

2019-11-14 18:16:12 -08:00

cpu

basic focal working

2009-05-10 23:51:20 +00:00

images

basic images for focal

2007-01-03 12:30:31 +00:00

pdf

2010-04-02 12:33:22 +00:00

pli

2010-06-07 20:36:11 +00:00

rom

2010-10-23 23:31:38 +00:00

rtl

synthesis

2010-10-26 11:20:13 +00:00

sim

boots tss/8

2010-04-02 12:32:05 +00:00

simhv36-1

added new tss8 source dirs

2016-01-02 16:39:18 +00:00

synth

2010-10-26 11:18:34 +00:00

tests

2010-06-05 17:09:48 +00:00

tss8

2011-11-25 13:03:04 +00:00

tss8_lcm2

Many tiny fixes. TSS/8 now runs from RK05! Long delay on program exit; suspect hung device.

2019-11-14 18:16:12 -08:00

tss8_uwm

added new tss8 source dirs

2016-01-02 16:39:18 +00:00

tss8.2

added new tss8 source dirs

2016-01-02 16:39:18 +00:00

tss8.23

added new tss8 source dirs

2016-01-02 16:39:18 +00:00

utils

Initial prep for fixing DSG0 to use RK05. Mostly notes, a few added comments.

2019-11-08 17:40:35 -08:00

initial

2007-01-02 16:24:48 +00:00

verif

verilator

2010-10-23 23:30:54 +00:00

verilator

2010-10-23 23:29:39 +00:00

xilinx

2010-04-24 10:35:11 +00:00

README.md

added README.md

2016-01-02 12:17:45 -05:00

README.md

cpus-pdp8

Verilog FPGA PDP-8/i cpu

A working PDP-8/i cpu with an RF08 disk emulator which uses a IDE disk as a backing store. It boots TSS/8.

Included are several versions of TSS/8 sources with utilites to build the base o/s from scratch.

A base file system with utilties is required as I have not yet found all the sources for the base utilties.

Languages

C 45.8%

Roff 26.9%

Verilog 16.4%

SystemVerilog 9.7%

Makefile 1.1%