From 13eb0f52bd73d50a4490188c52d77d1b4d866f09 Mon Sep 17 00:00:00 2001
From: Andrew Kay <git@ajk.me>
Date: Mon, 10 Feb 2020 22:26:39 -0600
Subject: [PATCH] Adding tx_inverted and updating pins

---
 interface2/rtl/coax_tx.v | 10 ++++++----
 interface2/rtl/pins.pcf  |  6 ++++--
 interface2/rtl/top.v     |  8 ++++++--
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/interface2/rtl/coax_tx.v b/interface2/rtl/coax_tx.v
index b5b6560..f0bb14d 100644
--- a/interface2/rtl/coax_tx.v
+++ b/interface2/rtl/coax_tx.v
@@ -3,9 +3,10 @@
 module coax_tx (
     input clk,
     input xxx,
-    output reg tx, // ??? why does thie have to be reg?
     output active,
-    output tx_delay
+    output reg tx, // ??? why does thie have to be reg?
+    output tx_delay,
+    output tx_inverted
 );
     parameter CLOCKS_PER_BIT = 8;
 
@@ -116,6 +117,8 @@ module coax_tx (
             tx_delay_reg <= { tx_delay_reg[0], tx };
     end
 
+    assign active = ((state == LINE_QUIESCE_1 && !bit_first_half) || state > LINE_QUIESCE_1);
+
     always @(*) // ??? is this best?
     begin
         tx <= 0;
@@ -140,7 +143,6 @@ module coax_tx (
             tx <= 1;
     end
 
-    assign active = ((state == LINE_QUIESCE_1 && !bit_first_half) || state > LINE_QUIESCE_1);
-
     assign tx_delay = active ? tx_delay_reg[1] : 0;
+    assign tx_inverted = active ? ~tx : 0;
 endmodule
diff --git a/interface2/rtl/pins.pcf b/interface2/rtl/pins.pcf
index df5357e..22790a8 100644
--- a/interface2/rtl/pins.pcf
+++ b/interface2/rtl/pins.pcf
@@ -1,5 +1,7 @@
-set_io --warn-no-port tx B8
-set_io --warn-no-port tx_active A9
+set_io --warn-no-port tx_active B1
+set_io --warn-no-port tx C2
+set_io --warn-no-port tx_delay C1
+set_io --warn-no-port tx_inverted D2
 
 # 16MHz clock
 set_io --warn-no-port clk_16mhz B2
diff --git a/interface2/rtl/top.v b/interface2/rtl/top.v
index 428147d..6225dbf 100644
--- a/interface2/rtl/top.v
+++ b/interface2/rtl/top.v
@@ -2,8 +2,10 @@
 
 module top (
     input clk_16mhz,
-    output tx,
     output tx_active,
+    output tx,
+    output tx_delay,
+    output tx_inverted,
     output usb_pu
 );
     // 19 MHz
@@ -27,8 +29,10 @@ module top (
     coax_tx coax_tx (
         .clk(clk_19mhz),
         .xxx(do_it),
+        .active(tx_active),
         .tx(tx),
-        .active(tx_active)
+        .tx_delay(tx_delay),
+        .tx_inverted(tx_inverted)
     );
 
     wire do_it;