New coax_tx_rx_frontend and coax_rx_blanker modules

interface2/fpga/tests/Makefile

@@ -12,6 +12,8 @@ coax_rx_tb: coax_rx_tb.v $(RTL)/coax_rx.v $(RTL)/coax_rx_ss_detector.v
 coax_tx_bit_timer_tb: coax_tx_bit_timer_tb.v $(RTL)/coax_tx_bit_timer.v
 coax_tx_distorter_tb: coax_tx_distorter_tb.v $(RTL)/coax_tx_distorter.v
 coax_tx_tb: coax_tx_tb.v $(RTL)/coax_tx.v $(RTL)/coax_tx_bit_timer.v
+coax_rx_blanker_tb: coax_rx_blanker_tb.v $(RTL)/coax_rx_blanker.v
+coax_tx_rx_frontend_tb: coax_tx_rx_frontend_tb.v $(RTL)/coax_tx_rx_frontend.v $(RTL)/coax_tx_distorter.v $(RTL)/coax_rx_blanker.v
 control_tb: control_tb.v $(RTL)/control.v $(RTL)/coax_buffered_tx.v $(RTL)/coax_tx.v $(RTL)/coax_tx_bit_timer.v $(RTL)/coax_buffer.v $(RTL)/third_party/*.v
 regression_memorex_tb: regression_memorex_tb.v $(RTL)/coax_rx.v $(RTL)/coax_rx_ss_detector.v
 

interface2/fpga/tests/coax_rx_blanker_tb.v

@@ -0,0 +1,117 @@
+`default_nettype none
+
+`include "assert.v"
+
+module coax_rx_blanker_tb;
+    reg clk = 0;
+
+    initial
+    begin
+        forever
+        begin
+            #1 clk <= ~clk;
+        end
+    end
+
+    reg reset = 0;
+    reg enable = 0;
+    reg rx_input = 0;
+    reg tx_active = 0;
+
+    coax_rx_blanker #(
+        .DELAY_CLOCKS(6)
+    ) dut (
+        .clk(clk),
+        .reset(reset),
+        .enable(enable),
+        .rx_input(rx_input),
+        .tx_active(tx_active)
+    );
+
+    initial
+    begin
+        $dumpfile("coax_rx_blanker_tb.vcd");
+        $dumpvars(0, coax_rx_blanker_tb);
+
+        test_not_enabled;
+        test_enabled_tx_not_active;
+        test_enabled_tx_active;
+
+        $finish;
+    end
+
+    task test_not_enabled;
+    begin
+        $display("START: test_not_enabled");
+
+        enable = 0;
+        rx_input = 1;
+
+        #4;
+
+        `assert_high(dut.rx_output, "rx_output should be HIGH");
+
+        rx_input = 0;
+
+        #4;
+
+        `assert_low(dut.rx_output, "rx_output should be LOW");
+
+        #16;
+
+        $display("END: test_not_enabled");
+    end
+    endtask
+
+    task test_enabled_tx_not_active;
+    begin
+        $display("START: test_enabled_tx_not_active");
+
+        enable = 1;
+        rx_input = 1;
+        tx_active = 0;
+
+        #4;
+
+        `assert_high(dut.rx_output, "rx_output should be HIGH");
+
+        rx_input = 0;
+
+        #4;
+
+        `assert_low(dut.rx_output, "rx_output should be LOW");
+
+        #16;
+
+        $display("END: test_enabled_tx_not_active");
+    end
+    endtask
+
+    task test_enabled_tx_active;
+    begin
+        $display("START: test_enabled_tx_active");
+
+        enable = 1;
+        rx_input = 1;
+        tx_active = 1;
+
+        #4;
+
+        `assert_low(dut.rx_output, "rx_output should be LOW");
+
+        tx_active = 0;
+
+        #4;
+
+        `assert_low(dut.rx_output, "rx_output should be LOW");
+
+        #12;
+
+        `assert_high(dut.rx_output, "rx_output should be HIGH");
+
+        #16;
+
+        $display("END: test_enabled_tx_active");
+    end
+    endtask
+endmodule

interface2/fpga/tests/coax_tx_rx_frontend_tb.v

@@ -0,0 +1,88 @@
+`default_nettype none
+
+`include "assert.v"
+
+module coax_tx_rx_frontend_tb;
+    reg clk = 0;
+
+    initial
+    begin
+        forever
+        begin
+            #1 clk <= ~clk;
+        end
+    end
+
+    reg reset = 0;
+    reg loopback = 0;
+    reg tx_active_input = 0;
+    reg tx_input = 0;
+    reg rx_input = 0;
+
+    coax_tx_rx_frontend #(
+        .CLOCKS_PER_BIT(8)
+    ) dut (
+        .clk(clk),
+        .reset(reset),
+        .loopback(loopback),
+        .tx_active_input(tx_active_input),
+        .tx_input(tx_input),
+        .rx_input(rx_input)
+    );
+
+    initial
+    begin
+        $dumpfile("coax_tx_rx_frontend_tb.vcd");
+        $dumpvars(0, coax_tx_rx_frontend_tb);
+
+        test_loopback;
+        test_not_loopback;
+
+        $finish;
+    end
+
+    task test_loopback;
+    begin
+        $display("START: test_loopback");
+
+        loopback = 1;
+        tx_active_input = 1;
+        tx_input = 1;
+        rx_input = 0;
+
+        #16;
+
+        tx_active_input = 0;
+        tx_input = 0;
+
+        #8;
+
+        loopback = 0;
+
+        #16;
+
+        $display("END: test_loopback");
+    end
+    endtask
+
+    task test_not_loopback;
+    begin
+        $display("START: test_not_loopback");
+
+        loopback = 0;
+        tx_active_input = 1;
+        tx_input = 1;
+        rx_input = 1;
+
+        #16;
+
+        tx_active_input = 0;
+        tx_input = 0;
+        rx_input = 0;
+
+        #16;
+
+        $display("END: test_not_loopback");
+    end
+    endtask
+endmodule