From 28fc1c0cef2a18e53ef73897767d1a8472c6750a Mon Sep 17 00:00:00 2001 From: Andrew Kay Date: Thu, 9 Jul 2020 07:50:24 -0500 Subject: [PATCH] Add distortion --- interface2/rtl/Makefile | 2 +- interface2/rtl/coax_tx.v | 35 +++++++++++----- interface2/rtl/coax_tx_distorter.v | 39 ++++++++++++++++++ interface2/rtl/pins.pcf | 4 +- interface2/rtl/top.v | 25 +++++++++--- interface2/tests/Makefile | 3 +- interface2/tests/coax_tx_distorter_tb.v | 54 +++++++++++++++++++++++++ 7 files changed, 142 insertions(+), 20 deletions(-) create mode 100644 interface2/rtl/coax_tx_distorter.v create mode 100644 interface2/tests/coax_tx_distorter_tb.v diff --git a/interface2/rtl/Makefile b/interface2/rtl/Makefile index f2d33fa..0629cbb 100644 --- a/interface2/rtl/Makefile +++ b/interface2/rtl/Makefile @@ -5,7 +5,7 @@ TINYPROG ?= tinyprog all: top.bin -top.json: top.v coax_tx_bit_timer.v coax_tx.v coax_rx_bit_timer.v coax_rx.v +top.json: top.v coax_tx_bit_timer.v coax_tx.v coax_tx_distorter.v coax_rx_bit_timer.v coax_rx.v prog: top.bin $(TINYPROG) -p top.bin diff --git a/interface2/rtl/coax_tx.v b/interface2/rtl/coax_tx.v index b511133..112635c 100644 --- a/interface2/rtl/coax_tx.v +++ b/interface2/rtl/coax_tx.v @@ -20,12 +20,13 @@ module coax_tx ( localparam START_SEQUENCE_6 = 6; localparam START_SEQUENCE_7 = 7; localparam START_SEQUENCE_8 = 8; - localparam SYNC_BIT = 9; - localparam DATA_BIT = 10; - localparam PARITY_BIT = 11; - localparam END_SEQUENCE_1 = 12; - localparam END_SEQUENCE_2 = 13; - localparam END_SEQUENCE_3 = 14; + localparam START_SEQUENCE_9 = 9; + localparam SYNC_BIT = 10; + localparam DATA_BIT = 11; + localparam PARITY_BIT = 12; + localparam END_SEQUENCE_1 = 13; + localparam END_SEQUENCE_2 = 14; + localparam END_SEQUENCE_3 = 15; reg [3:0] state = IDLE; reg [3:0] next_state; @@ -106,10 +107,14 @@ module coax_tx ( START_SEQUENCE_1: begin - next_tx = first_half ? 0 : 1; + next_tx = 1; - if (last_clock) + // TODO... off by 1 + if (second_half) + begin + next_bit_timer_reset = 1; next_state = START_SEQUENCE_2; + end end START_SEQUENCE_2: @@ -146,7 +151,7 @@ module coax_tx ( START_SEQUENCE_6: begin - next_tx = 0; + next_tx = first_half ? 0 : 1; if (last_clock) next_state = START_SEQUENCE_7; @@ -154,13 +159,21 @@ module coax_tx ( START_SEQUENCE_7: begin - next_tx = first_half ? 0 : 1; + next_tx = 0; if (last_clock) next_state = START_SEQUENCE_8; end START_SEQUENCE_8: + begin + next_tx = first_half ? 0 : 1; + + if (last_clock) + next_state = START_SEQUENCE_9; + end + + START_SEQUENCE_9: begin next_tx = 1; @@ -291,5 +304,5 @@ module coax_tx ( previous_load <= load; end - assign full = holding_data_full; + assign full = holding_data_full; // TODO: also after bit 10 if holding is empty... endmodule diff --git a/interface2/rtl/coax_tx_distorter.v b/interface2/rtl/coax_tx_distorter.v new file mode 100644 index 0000000..1964817 --- /dev/null +++ b/interface2/rtl/coax_tx_distorter.v @@ -0,0 +1,39 @@ +`default_nettype none + +module coax_tx_distorter ( + input clk, + input active_input, + input tx_input, + output reg active_output, + output reg tx_output, + output reg tx_delay, + output reg tx_inverted +); + parameter CLOCKS_PER_BIT = 8; + + localparam DELAY_CLOCKS = CLOCKS_PER_BIT / 4; + + reg [DELAY_CLOCKS-1:0] tx_delay_buffer = { (DELAY_CLOCKS){1'b1} }; + + always @(posedge clk) + begin + if (active_input) + begin + tx_delay_buffer <= { tx_delay_buffer[DELAY_CLOCKS-1:0], tx_input }; + + active_output <= active_input; + tx_output <= tx_input; + tx_delay <= tx_delay_buffer[DELAY_CLOCKS-1]; + tx_inverted <= ~tx_input; + end + else + begin + tx_delay_buffer <= { (DELAY_CLOCKS){1'b1} }; + + active_output <= 0; + tx_output <= 0; + tx_delay <= 0; + tx_inverted <= 0; + end + end +endmodule diff --git a/interface2/rtl/pins.pcf b/interface2/rtl/pins.pcf index 4aa3394..056b114 100644 --- a/interface2/rtl/pins.pcf +++ b/interface2/rtl/pins.pcf @@ -5,8 +5,8 @@ set_io --warn-no-port reset D2 # 6 # Transmitter set_io --warn-no-port tx_active A2 # 1 -#set_io --warn-no-port tx_inverted A1 # 2 -#set_io --warn-no-port tx_delay B1 # 3 +set_io --warn-no-port tx_inverted A1 # 2 +set_io --warn-no-port tx_delay B1 # 3 set_io --warn-no-port tx_load D1 # 7 set_io --warn-no-port tx_full E2 # 8 diff --git a/interface2/rtl/top.v b/interface2/rtl/top.v index 217987a..da1dfba 100644 --- a/interface2/rtl/top.v +++ b/interface2/rtl/top.v @@ -7,8 +7,8 @@ module top ( // Transmitter output tx_active, - // tx_inverted - // tx_delay + output tx_delay, + output tx_inverted, input tx_load, output tx_full, @@ -66,7 +66,8 @@ module top ( rx_read_1 <= rx_read_0; end - wire tx; + wire tx_active_undistorted; + wire tx_undistorted; wire [9:0] tx_data; assign tx_data = data; @@ -76,13 +77,27 @@ module top ( ) coax_tx ( .clk(clk_38mhz), .reset(reset), - .active(tx_active), - .tx(tx), + .active(tx_active_undistorted), + .tx(tx_undistorted), .data(tx_data), .load(tx_load_1), .full(tx_full) ); + wire tx; + + coax_tx_distorter #( + .CLOCKS_PER_BIT(16) + ) coax_tx_distorter ( + .clk(clk_38mhz), + .active_input(tx_active_undistorted), + .tx_input(tx_undistorted), + .active_output(tx_active), + .tx_output(tx), + .tx_delay(tx_delay), + .tx_inverted(tx_inverted) + ); + wire [9:0] rx_data; coax_rx #( diff --git a/interface2/tests/Makefile b/interface2/tests/Makefile index 8630512..d2e8598 100644 --- a/interface2/tests/Makefile +++ b/interface2/tests/Makefile @@ -3,10 +3,11 @@ VVP ?= vvp RTL = ../rtl -all: coax_tx_bit_timer_tb.vcd coax_tx_tb.vcd coax_rx_bit_timer_tb.vcd coax_rx_tb.vcd +all: coax_tx_bit_timer_tb.vcd coax_tx_tb.vcd coax_tx_distorter_tb.vcd coax_rx_bit_timer_tb.vcd coax_rx_tb.vcd coax_tx_bit_timer_tb: coax_tx_bit_timer_tb.v $(RTL)/coax_tx_bit_timer.v coax_tx_tb: coax_tx_tb.v $(RTL)/coax_tx.v $(RTL)/coax_tx_bit_timer.v +coax_tx_distorter_tb: coax_tx_distorter_tb.v $(RTL)/coax_tx_distorter.v coax_rx_bit_timer_tb: coax_rx_bit_timer_tb.v $(RTL)/coax_rx_bit_timer.v coax_rx_tb: coax_rx_tb.v $(RTL)/coax_rx.v $(RTL)/coax_rx_bit_timer.v diff --git a/interface2/tests/coax_tx_distorter_tb.v b/interface2/tests/coax_tx_distorter_tb.v new file mode 100644 index 0000000..5787377 --- /dev/null +++ b/interface2/tests/coax_tx_distorter_tb.v @@ -0,0 +1,54 @@ +`default_nettype none + +module coax_tx_distorter_tb; + reg clk = 0; + + initial + begin + forever + begin + #1 clk <= ~clk; + end + end + + reg active_input = 0; + reg tx_input = 0; + + coax_tx_distorter #( + .CLOCKS_PER_BIT(8) + ) dut ( + .clk(clk), + .active_input(active_input), + .tx_input(tx_input) + ); + + initial + begin + $dumpfile("coax_tx_distorter_tb.vcd"); + $dumpvars(0, coax_tx_distorter_tb); + + #16; + + active_input = 1; + + tx_input = 1; + #8; + + tx_input = 0; + #8; + tx_input = 1; + #8; + + tx_input = 0; + #8; + tx_input = 1; + #8; + tx_input = 0; + + active_input = 0; + + #32; + + $finish; + end +endmodule