From 2bf4c851265dbf5f278f214a249eda6ad82cec88 Mon Sep 17 00:00:00 2001 From: Andrew Kay Date: Sun, 5 Jul 2020 13:46:45 -0500 Subject: [PATCH] More work in progress --- interface2/rtl/coax_rx.v | 79 ++++++++++++-- interface2/tests/coax_rx_tb.v | 188 ++++++++++++++++++++++++++++++---- 2 files changed, 239 insertions(+), 28 deletions(-) diff --git a/interface2/rtl/coax_rx.v b/interface2/rtl/coax_rx.v index 4dcc3a6..5e1fc65 100644 --- a/interface2/rtl/coax_rx.v +++ b/interface2/rtl/coax_rx.v @@ -10,6 +10,9 @@ module coax_rx ( ); parameter CLOCKS_PER_BIT = 8; + localparam LOSS_OF_MID_BIT_TRANSITION_ERROR = 10'b0000000001; + localparam PARITY_ERROR = 10'b0000000010; + localparam IDLE = 0; localparam START_SEQUENCE_1 = 1; localparam START_SEQUENCE_2 = 2; @@ -21,7 +24,8 @@ module coax_rx ( localparam START_SEQUENCE_8 = 8; localparam START_SEQUENCE_9 = 9; localparam SYNC_BIT = 10; - localparam DATA = 11; + localparam DATA_BIT = 11; + localparam PARITY_BIT = 12; localparam ERROR = 50; // TODO: size... @@ -38,6 +42,11 @@ module coax_rx ( reg [9:0] next_data; + reg [9:0] xxx_data; + reg [9:0] next_xxx_data; + reg [3:0] bit_counter = 0; + reg [3:0] next_bit_counter; + wire sample; wire synchronized; @@ -58,7 +67,10 @@ module coax_rx ( next_bit_timer_reset = 0; - next_data = 10'b0000000000; + next_data = data; + + next_bit_counter = bit_counter; + next_xxx_data = xxx_data; case (state) IDLE: @@ -169,7 +181,7 @@ module coax_rx ( if (sample && synchronized) begin if (rx) - next_state = DATA; + next_state = DATA_BIT; else next_state = IDLE; end @@ -181,20 +193,65 @@ module coax_rx ( SYNC_BIT: begin - // TODO + if (sample) + begin + if (synchronized) + begin + // ... + end + else + begin + next_data = LOSS_OF_MID_BIT_TRANSITION_ERROR; + next_state = ERROR; + end + end end - DATA: + DATA_BIT: begin if (sample) begin if (synchronized) begin - // TODO + next_xxx_data = { xxx_data[8:0], rx }; + + if (bit_counter < 9) + begin + next_bit_counter = bit_counter + 1; + end + else + begin + next_state = PARITY_BIT; + end end else begin - next_data = 10'b0000000001; // TODO: LOSS OF MID-BIT TRANSITION + next_data = LOSS_OF_MID_BIT_TRANSITION_ERROR; + next_state = ERROR; + end + end + end + + PARITY_BIT: + begin + if (sample) + begin + if (synchronized) + begin + // Even parity includes the sync bit. + if (rx == ^{ 1'b1, xxx_data }) + begin + next_state = SYNC_BIT; + end + else + begin + next_data = PARITY_ERROR; + next_state = ERROR; + end + end + else + begin + next_data = LOSS_OF_MID_BIT_TRANSITION_ERROR; next_state = ERROR; end end @@ -215,6 +272,9 @@ module coax_rx ( data <= next_data; + bit_counter <= next_bit_counter; + xxx_data <= next_xxx_data; + if (reset) begin bit_timer_reset = 1; @@ -223,12 +283,15 @@ module coax_rx ( state <= IDLE; data <= 10'b0000000000; + + bit_counter <= 0; + xxx_data <= 10'b0000000000; end previous_rx <= rx; previous_state <= state; end - assign active = (state >= SYNC_BIT && state <= DATA); + assign active = (state >= SYNC_BIT && state <= PARITY_BIT); assign error = (state == ERROR); endmodule diff --git a/interface2/tests/coax_rx_tb.v b/interface2/tests/coax_rx_tb.v index c7d57d9..fed01da 100644 --- a/interface2/tests/coax_rx_tb.v +++ b/interface2/tests/coax_rx_tb.v @@ -26,6 +26,7 @@ module coax_rx_tb; $dumpfile("coax_rx_tb.vcd"); $dumpvars(0, coax_rx_tb); + /* test_1; test_2; test_3; @@ -36,6 +37,11 @@ module coax_rx_tb; test_8; test_9; test_10; + test_11; + test_12; + test_13; + */ + test_14; $finish; end @@ -44,13 +50,13 @@ module coax_rx_tb; begin $display("START: test_1"); - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); dut_reset; #8; - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); $display("END: test_1"); end @@ -60,13 +66,13 @@ module coax_rx_tb; begin $display("START: test_2"); - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); rx = 1; #64; - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); $display("END: test_2"); end @@ -76,13 +82,13 @@ module coax_rx_tb; begin $display("START: test_3"); - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); rx_bit(1); #64; - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); $display("END: test_3"); end @@ -92,14 +98,14 @@ module coax_rx_tb; begin $display("START: test_4"); - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); rx_bit(1); rx_bit(1); #64; - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); $display("END: test_4"); end @@ -109,7 +115,7 @@ module coax_rx_tb; begin $display("START: test_5"); - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); rx_bit(1); rx_bit(1); @@ -117,7 +123,7 @@ module coax_rx_tb; #64; - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); $display("END: test_5"); end @@ -127,7 +133,7 @@ module coax_rx_tb; begin $display("START: test_6"); - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); rx_bit(1); rx_bit(1); @@ -136,7 +142,7 @@ module coax_rx_tb; #64; - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); $display("END: test_6"); end @@ -146,7 +152,7 @@ module coax_rx_tb; begin $display("START: test_7"); - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); rx_bit(1); rx_bit(1); @@ -156,7 +162,7 @@ module coax_rx_tb; #64; - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); $display("END: test_7"); end @@ -166,7 +172,7 @@ module coax_rx_tb; begin $display("START: test_8"); - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); rx_bit(1); rx_bit(1); @@ -180,7 +186,7 @@ module coax_rx_tb; #64; - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); $display("END: test_8"); end @@ -190,7 +196,7 @@ module coax_rx_tb; begin $display("START: test_9"); - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); rx_start_sequence; @@ -198,7 +204,7 @@ module coax_rx_tb; #64; - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); $display("END: test_9"); end @@ -208,7 +214,7 @@ module coax_rx_tb; begin $display("START: test_10"); - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); rx_start_sequence; rx_bit(1); // SYNC_BIT @@ -218,17 +224,159 @@ module coax_rx_tb; `assert_equal(dut.state, dut.ERROR, "State should be ERROR"); `assert_high(dut.error, "error should be HIGH"); + `assert_equal(dut.data, dut.LOSS_OF_MID_BIT_TRANSITION_ERROR, "data should be LOSS_OF_MID_BIT_TRANSITION_ERROR"); dut_reset; #16; - `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); $display("END: test_10"); end endtask + task test_11; + begin + $display("START: test_11"); + + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); + + rx_start_sequence; + rx_bit(1); // SYNC_BIT + rx_bit(0); // MSB DATA_BIT + rx_bit(1); + rx_bit(1); + rx_bit(0); + rx_bit(1); + + #64; + + `assert_equal(dut.state, dut.ERROR, "State should be ERROR"); + + `assert_high(dut.error, "error should be HIGH"); + `assert_equal(dut.data, dut.LOSS_OF_MID_BIT_TRANSITION_ERROR, "data should be LOSS_OF_MID_BIT_TRANSITION_ERROR"); + + dut_reset; + + #16; + + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); + + $display("END: test_11"); + end + endtask + + task test_12; + begin + $display("START: test_12"); + + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); + + rx_start_sequence; + rx_bit(1); // SYNC_BIT + rx_bit(0); // MSB DATA_BIT + rx_bit(1); + rx_bit(1); + rx_bit(0); + rx_bit(1); + rx_bit(1); + rx_bit(0); + rx_bit(0); + rx_bit(1); + rx_bit(1); // LSB DATA_BIT + + #64; + + `assert_equal(dut.state, dut.ERROR, "State should be ERROR"); + + `assert_high(dut.error, "error should be HIGH"); + `assert_equal(dut.data, dut.LOSS_OF_MID_BIT_TRANSITION_ERROR, "data should be LOSS_OF_MID_BIT_TRANSITION_ERROR"); + + dut_reset; + + #16; + + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); + + $display("END: test_12"); + end + endtask + + task test_13; + begin + $display("START: test_13"); + + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); + + rx_start_sequence; + rx_bit(1); // SYNC_BIT + rx_bit(0); // MSB DATA_BIT + rx_bit(1); + rx_bit(1); + rx_bit(0); + rx_bit(1); + rx_bit(1); + rx_bit(0); + rx_bit(0); + rx_bit(1); + rx_bit(1); // LSB DATA_BIT + rx_bit(0); // PARITY_BIT + + #64; + + `assert_equal(dut.state, dut.ERROR, "State should be ERROR"); + + `assert_high(dut.error, "error should be HIGH"); + `assert_equal(dut.data, dut.PARITY_ERROR, "data should be PARITY_ERROR"); + + dut_reset; + + #16; + + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); + + $display("END: test_13"); + end + endtask + + task test_14; + begin + $display("START: test_14"); + + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); + + rx_start_sequence; + rx_bit(1); // SYNC_BIT + rx_bit(0); // MSB DATA_BIT + rx_bit(1); + rx_bit(1); + rx_bit(0); + rx_bit(1); + rx_bit(1); + rx_bit(0); + rx_bit(0); + rx_bit(1); + rx_bit(1); // LSB DATA_BIT + rx_bit(1); // PARITY_BIT + + #64; + + `assert_equal(dut.state, dut.ERROR, "State should be ERROR"); + + `assert_high(dut.error, "error should be HIGH"); + `assert_equal(dut.data, dut.LOSS_OF_MID_BIT_TRANSITION_ERROR, "data should be LOSS_OF_MID_BIT_TRANSITION_ERROR"); + + dut_reset; + + #16; + + `assert_equal(dut.state, dut.IDLE, "state should be IDLE"); + + $display("END: test_14"); + end + endtask + task dut_reset; begin reset = 1;