diff --git a/interface2/rtl/Makefile b/interface2/rtl/Makefile
index 141d049..f2d33fa 100644
--- a/interface2/rtl/Makefile
+++ b/interface2/rtl/Makefile
@@ -5,7 +5,7 @@ TINYPROG ?= tinyprog
 
 all: top.bin
 
-top.json: top.v coax_rx_bit_timer.v coax_rx.v
+top.json: top.v coax_tx_bit_timer.v coax_tx.v coax_rx_bit_timer.v coax_rx.v
 
 prog: top.bin
 	$(TINYPROG) -p top.bin
diff --git a/interface2/rtl/pins.pcf b/interface2/rtl/pins.pcf
index df77d55..4aa3394 100644
--- a/interface2/rtl/pins.pcf
+++ b/interface2/rtl/pins.pcf
@@ -1,20 +1,18 @@
 # 16MHz clock
 set_io --warn-no-port clk_16mhz B2
 
+set_io --warn-no-port reset D2 # 6
+
 # Transmitter
-#set_io --warn-no-port tx_active A2 # 1
+set_io --warn-no-port tx_active A2 # 1
 #set_io --warn-no-port tx_inverted A1 # 2
 #set_io --warn-no-port tx_delay B1 # 3
-
-#set_io --warn-no-port tx_load D2 # 6
-#set_io --warn-no-port tx_full D1 # 7
+set_io --warn-no-port tx_load D1 # 7
+set_io --warn-no-port tx_full E2 # 8
 
 # Receiver
 set_io --warn-no-port rx C2 # 4
-
-set_io --warn-no-port reset E1 # 9
-
-#set_io --warn-no-port rx_enable E1 # 9
+set_io --warn-no-port rx_enable E1 # 9
 set_io --warn-no-port rx_active G2 # 10
 set_io --warn-no-port rx_error H1 # 11
 set_io --warn-no-port rx_data_available J1 # 12
diff --git a/interface2/rtl/top.v b/interface2/rtl/top.v
index c1fbcde..217987a 100644
--- a/interface2/rtl/top.v
+++ b/interface2/rtl/top.v
@@ -3,8 +3,18 @@
 module top (
     input clk_16mhz,
 
+    input reset,
+
+    // Transmitter
+    output tx_active,
+    // tx_inverted
+    // tx_delay
+    input tx_load,
+    output tx_full,
+
     // Receiver
     input rx,
+    input rx_enable,
     output rx_active,
     output rx_error,
     output rx_data_available,
@@ -13,7 +23,6 @@ module top (
     // Shared data bus
     inout [9:0] data,
 
-    input reset,
     output debug,
 
     output usb_pu
@@ -36,6 +45,9 @@ module top (
         .PLLOUTCORE(clk_38mhz)
     );
 
+    reg tx_load_0 = 0;
+    reg tx_load_1 = 0;
+
     reg rx_0 = 0;
     reg rx_1 = 0;
 
@@ -44,6 +56,9 @@ module top (
 
     always @(posedge clk_38mhz)
     begin
+        tx_load_0 <= tx_load;
+        tx_load_1 <= tx_load_0;
+
         rx_0 <= rx;
         rx_1 <= rx_0;
 
@@ -51,6 +66,23 @@ module top (
         rx_read_1 <= rx_read_0;
     end
 
+    wire tx;
+    wire [9:0] tx_data;
+
+    assign tx_data = data;
+
+    coax_tx #(
+        .CLOCKS_PER_BIT(16)
+    ) coax_tx (
+        .clk(clk_38mhz),
+        .reset(reset),
+        .active(tx_active),
+        .tx(tx),
+        .data(tx_data),
+        .load(tx_load_1),
+        .full(tx_full)
+    );
+
     wire [9:0] rx_data;
 
     coax_rx #(
@@ -66,9 +98,9 @@ module top (
         .read(rx_read_1)
     );
 
-    assign data = rx_data;
+    assign data = rx_enable ? rx_data : 10'bzzzzzzzzzz;
 
-    assign debug = rx_1;
+    assign debug = rx_enable ? rx_1 : tx;
 
     assign usb_pu = 0;
 endmodule