Add data, data_available and data_read

interface2/rtl/coax_rx.v

@@ -3,7 +3,10 @@
 module coax_rx (
     input clk,
     input rx,
-    output active
+    input data_read,
+    output active,
+    output reg [9:0] data = 10'b0,
+    output reg data_available = 0
 );
     parameter CLOCKS_PER_BIT = 8;
 
@@ -90,7 +93,7 @@ module coax_rx (
                 CODE_VIOLATION_2: next_state <= rx_1 ? CODE_VIOLATION_3A: IDLE;
                 SYNC_BIT: next_state <= rx_1 ? DATA : /* TODO: ERROR */ IDLE;
                 DATA: next_state <= input_data_counter == 9 ? PARITY_BIT : DATA;
-                PARITY_BIT: next_state <= rx_1 == parity_bit ? END_1 : /* TODO: ERROR */ IDLE;
+                PARITY_BIT: next_state <= rx_1 == parity_bit ? END_1 : /* TODO: ERROR... also check for overflow of data */ IDLE;
                 END_1: next_state <= rx_1 ? DATA : IDLE; // TODO: END_2
             endcase
         end
@@ -101,6 +104,9 @@ module coax_rx (
         rx_0 <= rx;
         rx_1 <= rx_0;
 
+        if (data_read && data_available)
+            data_available <= 0;
+
         if (state == DATA)
         begin
             if (state != previous_state)
@@ -119,6 +125,11 @@ module coax_rx (
                     parity_bit <= ~parity_bit;
             end
         end
+        else if (state == END_1 && state != previous_state)
+        begin
+            data <= input_data;
+            data_available <= 1;
+        end
 
         state <= next_state;
         previous_state <= state;

interface2/tests/coax_rx_tb.v

@@ -24,11 +24,16 @@ module coax_rx_tb();
         .tx(tx_tx)
     );
 
+    reg rx_data_read = 0;
+    wire rx_data_available;
+
     coax_rx #(
         .CLOCKS_PER_BIT(8)
     ) dut (
         .clk(clk),
-        .rx(tx_tx)
+        .rx(tx_tx),
+        .data_read(rx_data_read),
+        .data_available(rx_data_available)
     );
 
     initial
@@ -48,7 +53,17 @@ module coax_rx_tb();
         tx_load = 1;
         #2 tx_load = 0;
 
-        repeat(1000) @(posedge clk);
+        repeat(200) @(posedge clk);
+
+        rx_data_read = 1;
+        #4 rx_data_read = 0;
+
+        repeat(100) @(posedge clk);
+
+        rx_data_read = 1;
+        #4 rx_data_read = 0;
+
+        repeat(100) @(posedge clk);
 
         $finish;
     end