Add FPGA tests to interface2 build workflow

interface2/fpga/tests/Makefile

@@ -16,7 +16,7 @@ coax_tx_tb: coax_tx_tb.v $(RTL)/coax_tx.v $(RTL)/coax_tx_bit_timer.v
 control_tb: control_tb.v $(RTL)/control.v $(RTL)/coax_buffered_tx.v $(RTL)/coax_tx.v $(RTL)/coax_tx_bit_timer.v $(RTL)/coax_buffer.v $(RTL)/third_party/*.v
 
 test: $(TESTS)
-	$(foreach tb,$(TESTS),./run_test.sh $(tb);)
+	./run_tests.sh
 
 clean:
 	rm -f *_tb *.vcd

interface2/fpga/tests/assert.v

@@ -1,7 +1,7 @@
 `define assert_equal(actual, expected, message) \
     if ((actual) !== expected) \
     begin \
-        $display("[ASSERTION FAILURE] %m (%s:%0d): %s", `__FILE__, `__LINE__, message); \
+        $display("[FAIL:ASSERTION] %m (%s:%0d): %s", `__FILE__, `__LINE__, message); \
         $display("\tTime:     %0t", $time); \
         $display("\tExpected: %x", expected); \
         $display("\tActual:   %x", actual); \

interface2/fpga/tests/run_test.sh

@@ -1,7 +0,0 @@
-#!/bin/sh
-
-VVP=vvp
-
-echo "Running $1"
-
-${VVP} -N $1

interface2/fpga/tests/run_tests.sh

@@ -0,0 +1,19 @@
+#!/bin/bash
+
+VVP=vvp
+
+set -o pipefail
+
+ANY_FAILURES=0
+
+for TB in *_tb; do
+    echo "Running $TB"
+
+    ${VVP} -n $TB | awk "BEGIN{f=0} /^\[FAIL:/{f=1} 1; END{exit(f)}"
+
+    if [ $? != 0 ]; then
+        ANY_FAILURES=1
+    fi
+done
+
+exit $ANY_FAILURES