From 8dc730df8a89f90468f309f3d623be256574f791 Mon Sep 17 00:00:00 2001
From: Andrew Kay <git@ajk.me>
Date: Fri, 10 Jul 2020 22:15:53 -0500
Subject: [PATCH] Fix receiver start and end sequence detection

---
 interface2/rtl/coax_rx.v      | 23 +++++++++++------------
 interface2/tests/coax_rx_tb.v | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 12 deletions(-)

diff --git a/interface2/rtl/coax_rx.v b/interface2/rtl/coax_rx.v
index f310642..ab59c3e 100644
--- a/interface2/rtl/coax_rx.v
+++ b/interface2/rtl/coax_rx.v
@@ -99,17 +99,10 @@ module coax_rx (
         case (state)
             IDLE:
             begin
-                // TODO: should I move this to all the IDLE transitions?
-                if (previous_state != IDLE)
-                    next_bit_timer_reset = 1;
+                next_bit_timer_reset = 1;
 
-                if (rx != previous_rx)
-                begin
-                    if (rx && !previous_rx)
-                        next_state = START_SEQUENCE_1;
-                    else
-                        next_bit_timer_reset = 1;
-                end
+                if (!rx && previous_rx)
+                    next_state = START_SEQUENCE_1;
             end
 
             START_SEQUENCE_1:
@@ -121,6 +114,10 @@ module coax_rx (
                     else
                         next_state = IDLE;
                 end
+                else if (state_counter >= (CLOCKS_PER_BIT * 2))
+                begin
+                    next_state = IDLE;
+                end
             end
 
             START_SEQUENCE_2:
@@ -319,8 +316,10 @@ module coax_rx (
 
            END_SEQUENCE_2:
            begin
-               // TODO: Let's do more!
-               next_state = IDLE;
+               if (!rx)
+                   next_state = IDLE;
+               else if (state_counter >= (CLOCKS_PER_BIT * 2))
+                   next_state = IDLE;
            end
         endcase
     end
diff --git a/interface2/tests/coax_rx_tb.v b/interface2/tests/coax_rx_tb.v
index 5e07c96..dde130d 100644
--- a/interface2/tests/coax_rx_tb.v
+++ b/interface2/tests/coax_rx_tb.v
@@ -90,6 +90,10 @@ module coax_rx_tb;
 
         `assert_equal(dut.state, dut.IDLE, "state should be IDLE");
 
+        rx = 1;
+        #16;
+        rx = 0;
+
         rx_bit(1);
 
         #64;
@@ -106,6 +110,10 @@ module coax_rx_tb;
 
         `assert_equal(dut.state, dut.IDLE, "state should be IDLE");
 
+        rx = 1;
+        #16;
+        rx = 0;
+
         rx_bit(1);
         rx_bit(1);
 
@@ -123,6 +131,10 @@ module coax_rx_tb;
 
         `assert_equal(dut.state, dut.IDLE, "state should be IDLE");
 
+        rx = 1;
+        #16;
+        rx = 0;
+
         rx_bit(1);
         rx_bit(1);
         rx_bit(1);
@@ -141,6 +153,10 @@ module coax_rx_tb;
 
         `assert_equal(dut.state, dut.IDLE, "state should be IDLE");
 
+        rx = 1;
+        #16;
+        rx = 0;
+
         rx_bit(1);
         rx_bit(1);
         rx_bit(1);
@@ -160,6 +176,10 @@ module coax_rx_tb;
 
         `assert_equal(dut.state, dut.IDLE, "state should be IDLE");
 
+        rx = 1;
+        #16;
+        rx = 0;
+
         rx_bit(1);
         rx_bit(1);
         rx_bit(1);
@@ -180,6 +200,10 @@ module coax_rx_tb;
 
         `assert_equal(dut.state, dut.IDLE, "state should be IDLE");
 
+        rx = 1;
+        #16;
+        rx = 0;
+
         rx_bit(1);
         rx_bit(1);
         rx_bit(1);
@@ -194,6 +218,8 @@ module coax_rx_tb;
 
         `assert_equal(dut.state, dut.IDLE, "state should be IDLE");
 
+        rx = 0;
+
         $display("END: test_8");
     end
     endtask
@@ -530,6 +556,12 @@ module coax_rx_tb;
 
     task rx_start_sequence;
     begin
+        rx = 0;
+        #16;
+        rx = 1;
+        #16;
+        rx = 0;
+
         rx_bit(1);
         rx_bit(1);
         rx_bit(1);