From 90ddeb54d67c97d22f9ed451e472b762d7a5d84c Mon Sep 17 00:00:00 2001 From: Andrew Kay Date: Sun, 5 Jul 2020 13:00:46 -0500 Subject: [PATCH] Work in progress --- interface2/rtl/coax_rx.v | 74 ++++++++++++++--------------------- interface2/tests/assert.v | 14 +++++++ interface2/tests/coax_rx_tb.v | 68 +++++++++++++++++++++++++++----- 3 files changed, 102 insertions(+), 54 deletions(-) create mode 100644 interface2/tests/assert.v diff --git a/interface2/rtl/coax_rx.v b/interface2/rtl/coax_rx.v index 49c091a..4dcc3a6 100644 --- a/interface2/rtl/coax_rx.v +++ b/interface2/rtl/coax_rx.v @@ -4,7 +4,9 @@ module coax_rx ( input clk, input rx, input reset, - output active + output active, + output error, + output reg [9:0] data ); parameter CLOCKS_PER_BIT = 8; @@ -20,6 +22,7 @@ module coax_rx ( localparam START_SEQUENCE_9 = 9; localparam SYNC_BIT = 10; localparam DATA = 11; + localparam ERROR = 50; // TODO: size... reg [8:0] state = IDLE; @@ -33,6 +36,8 @@ module coax_rx ( reg bit_timer_reset = 0; reg next_bit_timer_reset; + reg [9:0] next_data; + wire sample; wire synchronized; @@ -53,6 +58,8 @@ module coax_rx ( next_bit_timer_reset = 0; + next_data = 10'b0000000000; + case (state) IDLE: begin @@ -130,20 +137,6 @@ module coax_rx ( next_state = START_SEQUENCE_7; else if (state_counter >= CLOCKS_PER_BIT) next_state = IDLE; - /* - if (sample) - begin - if (!rx) - begin - next_bit_timer_reset = 1; - next_state = START_SEQUENCE_7; - end - else - begin - next_state = IDLE; // NOT TESTED! - end - end - */ end START_SEQUENCE_7: @@ -152,12 +145,6 @@ module coax_rx ( next_state = START_SEQUENCE_8; else if (state_counter >= (CLOCKS_PER_BIT * 2)) next_state = IDLE; - /* - if (synchronized && sample && rx) - next_state = START_SEQUENCE_8; - else if (state_counter >= (CLOCKS_PER_BIT * 2)) - next_state = IDLE; - */ end START_SEQUENCE_8: @@ -171,44 +158,25 @@ module coax_rx ( begin next_state = IDLE; end - /* - if (sample) - begin - if (rx) - next_state = START_SEQUENCE_9; - else - next_state = IDLE; // NOT TESTED! - end - */ end START_SEQUENCE_9: begin - // This is really the first SYNC_BIT... + // This is really the first SYNC_BIT but we treat it + // differently and consider it part of the start + // sequence. if (sample && synchronized) begin if (rx) next_state = DATA; else - next_state = /* TODO: ERROR START SEQUENCE? */ IDLE; + next_state = IDLE; end else if (state_counter >= CLOCKS_PER_BIT) - begin - next_state = /* TODO: ERROR LOSS OF MID-BIT TRANSITION */ IDLE; - end - - /* - if (!rx) - begin - next_bit_timer_reset = 1; - next_state = SYNC_BIT; - end - else if (state_counter >= (CLOCKS_PER_BIT * 2)) begin next_state = IDLE; end - */ end SYNC_BIT: @@ -218,7 +186,18 @@ module coax_rx ( DATA: begin - // TODO + if (sample) + begin + if (synchronized) + begin + // TODO + end + else + begin + next_data = 10'b0000000001; // TODO: LOSS OF MID-BIT TRANSITION + next_state = ERROR; + end + end end endcase end @@ -234,12 +213,16 @@ module coax_rx ( bit_timer_reset <= next_bit_timer_reset; + data <= next_data; + if (reset) begin bit_timer_reset = 1; state_counter <= 0; state <= IDLE; + + data <= 10'b0000000000; end previous_rx <= rx; @@ -247,4 +230,5 @@ module coax_rx ( end assign active = (state >= SYNC_BIT && state <= DATA); + assign error = (state == ERROR); endmodule diff --git a/interface2/tests/assert.v b/interface2/tests/assert.v new file mode 100644 index 0000000..9b9f38f --- /dev/null +++ b/interface2/tests/assert.v @@ -0,0 +1,14 @@ +`define assert_equal(actual, expected, message) \ + if ((actual) !== expected) \ + begin \ + $display("[ASSERTION FAILURE] %m (%s:%0d): %s", `__FILE__, `__LINE__, message); \ + $display("\tTime: %0t", $time); \ + $display("\tExpected: %x", expected); \ + $display("\tActual: %x", actual); \ + end + +`define assert_high(actual, message) \ + `assert_equal(actual, 1, message) + +`define assert_low(actual, message) \ + `assert_equal(actual, 0, message) diff --git a/interface2/tests/coax_rx_tb.v b/interface2/tests/coax_rx_tb.v index 216ed8c..c7d57d9 100644 --- a/interface2/tests/coax_rx_tb.v +++ b/interface2/tests/coax_rx_tb.v @@ -1,5 +1,7 @@ `default_nettype none +`include "assert.v" + module coax_rx_tb; reg clk = 0; @@ -24,15 +26,15 @@ module coax_rx_tb; $dumpfile("coax_rx_tb.vcd"); $dumpvars(0, coax_rx_tb); - //test_1; - //test_2; - //test_3; - //test_4; - //test_5; - //test_6; - //test_7; - //test_8; - //test_9; + test_1; + test_2; + test_3; + test_4; + test_5; + test_6; + test_7; + test_8; + test_9; test_10; $finish; @@ -42,10 +44,14 @@ module coax_rx_tb; begin $display("START: test_1"); + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + dut_reset; #8; + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + $display("END: test_1"); end endtask @@ -54,10 +60,14 @@ module coax_rx_tb; begin $display("START: test_2"); + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + rx = 1; #64; + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + $display("END: test_2"); end endtask @@ -66,10 +76,14 @@ module coax_rx_tb; begin $display("START: test_3"); + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + rx_bit(1); #64; + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + $display("END: test_3"); end endtask @@ -78,11 +92,15 @@ module coax_rx_tb; begin $display("START: test_4"); + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + rx_bit(1); rx_bit(1); #64; + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + $display("END: test_4"); end endtask @@ -91,12 +109,16 @@ module coax_rx_tb; begin $display("START: test_5"); + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + rx_bit(1); rx_bit(1); rx_bit(1); #64; + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + $display("END: test_5"); end endtask @@ -105,6 +127,8 @@ module coax_rx_tb; begin $display("START: test_6"); + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + rx_bit(1); rx_bit(1); rx_bit(1); @@ -112,6 +136,8 @@ module coax_rx_tb; #64; + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + $display("END: test_6"); end endtask @@ -120,6 +146,8 @@ module coax_rx_tb; begin $display("START: test_7"); + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + rx_bit(1); rx_bit(1); rx_bit(1); @@ -128,6 +156,8 @@ module coax_rx_tb; #64; + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + $display("END: test_7"); end endtask @@ -136,6 +166,8 @@ module coax_rx_tb; begin $display("START: test_8"); + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + rx_bit(1); rx_bit(1); rx_bit(1); @@ -148,6 +180,8 @@ module coax_rx_tb; #64; + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + $display("END: test_8"); end endtask @@ -156,12 +190,16 @@ module coax_rx_tb; begin $display("START: test_9"); + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + rx_start_sequence; rx = 0; #64; + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + $display("END: test_9"); end endtask @@ -170,11 +208,23 @@ module coax_rx_tb; begin $display("START: test_10"); + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + rx_start_sequence; rx_bit(1); // SYNC_BIT #64; + `assert_equal(dut.state, dut.ERROR, "State should be ERROR"); + + `assert_high(dut.error, "error should be HIGH"); + + dut_reset; + + #16; + + `assert_equal(dut.state, dut.IDLE, "State should be IDLE"); + $display("END: test_10"); end endtask