github.com/lowobservable.coax
1
0
Fork 0
mirror of https://github.com/lowobservable/coax.git synced 2026-02-10 02:20:21 +00:00
Code Issues Projects Releases Wiki Activity

Add interface2

Browse Source
This commit is contained in:
Andrew Kay
2021-03-29 16:38:00 -05:00
parent fce3b4c273
commit 925830f0a4
107 changed files with 54855 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

161
interface2/fpga/rtl/third_party/fifo_sync_ram.v vendored Normal file
View File

@@ -0,0 +1,161 @@
// https://raw.githubusercontent.com/smunaut/ice40-playground/68ac87f6c458712a41d5b8e305d222849233ff00/cores/misc/rtl/fifo_sync_ram.v
/*
* fifo_sync_ram.v
*
* vim: ts=4 sw=4
*
* Copyright (C) 2019 Sylvain Munaut <tnt@246tNt.com>
* All rights reserved.
*
* BSD 3-clause, see LICENSE.bsd
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
module fifo_sync_ram #(
parameter integer DEPTH = 256,
parameter integer WIDTH = 16
)(
input wire [WIDTH-1:0] wr_data,
input wire wr_ena,
output wire wr_full,
output wire [WIDTH-1:0] rd_data,
input wire rd_ena,
output wire rd_empty,
input wire clk,
input wire rst
);
localparam AWIDTH = $clog2(DEPTH);
// Signals
// -------
// RAM
reg [AWIDTH-1:0] ram_wr_addr;
wire [ WIDTH-1:0] ram_wr_data;
wire ram_wr_ena;
reg [AWIDTH-1:0] ram_rd_addr;
wire [ WIDTH-1:0] ram_rd_data;
wire ram_rd_ena;
// Fill-level
reg [AWIDTH:0] level;
(* keep="true" *) wire lvl_dec;
(* keep="true" *) wire lvl_mov;
wire lvl_empty;
// Full
wire full_nxt;
reg full;
// Read logic
reg rd_valid;
// Fill level counter
// ------------------
// (counts the number of used words - 1)
always @(posedge clk or posedge rst)
if (rst)
level <= {(AWIDTH+1){1'b1}};
else
level <= level + { {AWIDTH{lvl_dec}}, lvl_mov };
assign lvl_dec = ram_rd_ena & ~ram_wr_ena;
assign lvl_mov = ram_rd_ena ^ ram_wr_ena;
assign lvl_empty = level[AWIDTH];
// Full flag generation
// --------------------
assign full_nxt = level == { 1'b0, {(AWIDTH-2){1'b1}}, 2'b01 };
always @(posedge clk or posedge rst)
if (rst)
full <= 1'b0;
else
full <= (full | (wr_ena & ~rd_ena & full_nxt)) & ~(rd_ena & ~wr_ena);
assign wr_full = full;
// Write
// -----
always @(posedge clk or posedge rst)
if (rst)
ram_wr_addr <= 0;
else if (ram_wr_ena)
ram_wr_addr <= ram_wr_addr + 1;
assign ram_wr_data = wr_data;
assign ram_wr_ena = wr_ena;
// Read
// ----
always @(posedge clk or posedge rst)
if (rst)
ram_rd_addr <= 0;
else if (ram_rd_ena)
ram_rd_addr <= ram_rd_addr + 1;
assign ram_rd_ena = (rd_ena | ~rd_valid) & ~lvl_empty;
always @(posedge clk or posedge rst)
if (rst)
rd_valid <= 1'b0;
else if (rd_ena | ~rd_valid)
rd_valid <= ~lvl_empty;
assign rd_data = ram_rd_data;
assign rd_empty = ~rd_valid;
// RAM
// ---
ram_sdp #(
.AWIDTH(AWIDTH),
.DWIDTH(WIDTH)
) ram_I (
.wr_addr(ram_wr_addr),
.wr_data(ram_wr_data),
.wr_ena(ram_wr_ena),
.rd_addr(ram_rd_addr),
.rd_data(ram_rd_data),
.rd_ena(ram_rd_ena),
.clk(clk)
);
endmodule // fifo_sync_ram

73
interface2/fpga/rtl/third_party/ram_sdp.v vendored Normal file
View File

@@ -0,0 +1,73 @@
// https://raw.githubusercontent.com/smunaut/ice40-playground/68ac87f6c458712a41d5b8e305d222849233ff00/cores/misc/rtl/ram_sdp.v
/*
* ram_sdp.v
*
* vim: ts=4 sw=4
*
* Copyright (C) 2019 Sylvain Munaut <tnt@246tNt.com>
* All rights reserved.
*
* BSD 3-clause, see LICENSE.bsd
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
module ram_sdp #(
parameter integer AWIDTH = 9,
parameter integer DWIDTH = 8
)(
input wire [AWIDTH-1:0] wr_addr,
input wire [DWIDTH-1:0] wr_data,
input wire wr_ena,
input wire [AWIDTH-1:0] rd_addr,
output reg [DWIDTH-1:0] rd_data,
input wire rd_ena,
input wire clk
);
// Signals
reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
`ifdef SIM
integer i;
initial
for (i=0; i<(1<<AWIDTH); i=i+1)
ram[i] = 0;
`endif
always @(posedge clk)
begin
// Read
if (rd_ena)
rd_data <= ram[rd_addr];
// Write
if (wr_ena)
ram[wr_addr] <= wr_data;
end
endmodule // ram_sdp