From 9dd8d37ef58415bd5bdab70a7a5cf07fff6c2ad5 Mon Sep 17 00:00:00 2001 From: Andrew Kay Date: Tue, 16 Jun 2020 16:53:53 -0500 Subject: [PATCH] wip --- interface2/rtl/Makefile | 2 +- interface2/rtl/coax_rx_bit_timer.v | 8 +- interface2/rtl/top.v | 26 + .../tests/coax_rx_bit_timer_tb.vcd_snapshot | 832 ++++++++++++++++++ 4 files changed, 863 insertions(+), 5 deletions(-) create mode 100644 interface2/tests/coax_rx_bit_timer_tb.vcd_snapshot diff --git a/interface2/rtl/Makefile b/interface2/rtl/Makefile index 9009a60..8ade63c 100644 --- a/interface2/rtl/Makefile +++ b/interface2/rtl/Makefile @@ -5,7 +5,7 @@ TINYPROG ?= tinyprog all: top.bin -top.json: top.v +top.json: top.v coax_rx_bit_timer.v prog: top.bin $(TINYPROG) -p top.bin diff --git a/interface2/rtl/coax_rx_bit_timer.v b/interface2/rtl/coax_rx_bit_timer.v index 3970699..c6a4291 100644 --- a/interface2/rtl/coax_rx_bit_timer.v +++ b/interface2/rtl/coax_rx_bit_timer.v @@ -47,7 +47,7 @@ module coax_rx_bit_timer( SYNCHRONIZED: begin - if (transition_counter < CLOCKS_PER_BIT * 1.25) + if (transition_counter < (CLOCKS_PER_BIT + (CLOCKS_PER_BIT / 4))) next_transition_counter = transition_counter + 1; else next_state = UNSYNCHRONIZED; @@ -59,13 +59,13 @@ module coax_rx_bit_timer( else next_bit_counter = 0; - if (rx != previous_rx && transition_counter > CLOCKS_PER_BIT / 2) + if (rx != previous_rx && transition_counter > (CLOCKS_PER_BIT / 2)) begin next_transition_counter = 0; next_bit_counter = CLOCKS_PER_BIT / 2; end - if (bit_counter == CLOCKS_PER_BIT * 0.75) + if (bit_counter == ((CLOCKS_PER_BIT / 4) * 3)) sample = 1; end @@ -76,7 +76,7 @@ module coax_rx_bit_timer( else next_bit_counter = 0; - if (bit_counter == CLOCKS_PER_BIT * 0.75) + if (bit_counter == ((CLOCKS_PER_BIT / 4) * 3)) sample = 1; end endcase diff --git a/interface2/rtl/top.v b/interface2/rtl/top.v index 6ad9388..56c93cd 100644 --- a/interface2/rtl/top.v +++ b/interface2/rtl/top.v @@ -3,6 +3,13 @@ module top ( input clk_16mhz, + // Receiver + input rx, + + input reset, + output sample, + output synchronized, + output usb_pu ); // 19 MHz @@ -23,5 +30,24 @@ module top ( .PLLOUTCORE(clk_19mhz) ); + reg rx_0 = 0; + reg rx_1 = 1; + + always @(posedge clk_19mhz) + begin + rx_0 <= rx; + rx_1 <= rx_0; + end + + coax_rx_bit_timer #( + .CLOCKS_PER_BIT(8) + ) rx_bit_timer ( + .clk(clk_19mhz), + .rx(rx_1), + .reset(reset), + .sample(sample), + .synchronized(synchronized) + ); + assign usb_pu = 0; endmodule diff --git a/interface2/tests/coax_rx_bit_timer_tb.vcd_snapshot b/interface2/tests/coax_rx_bit_timer_tb.vcd_snapshot new file mode 100644 index 0000000..bce01dc --- /dev/null +++ b/interface2/tests/coax_rx_bit_timer_tb.vcd_snapshot @@ -0,0 +1,832 @@ +$date + Mon Jun 15 21:59:45 2020 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module coax_rx_bit_timer_tb $end +$var wire 1 ! synchronized $end +$var wire 1 " sample $end +$var reg 1 # clk $end +$var reg 1 $ reset $end +$var reg 1 % rx $end +$scope module dut $end +$var wire 1 # clk $end +$var wire 1 $ reset $end +$var wire 1 % rx $end +$var reg 4 & bit_counter [3:0] $end +$var reg 4 ' next_bit_counter [3:0] $end +$var reg 2 ( next_state [1:0] $end +$var reg 5 ) next_transition_counter [4:0] $end +$var reg 1 * previous_rx $end +$var reg 1 " sample $end +$var reg 2 + state [1:0] $end +$var reg 1 ! synchronized $end +$var reg 5 , transition_counter [4:0] $end +$upscope $end +$scope task rx_bit $end +$var reg 1 - bit $end +$upscope $end +$scope task rx_bit_custom $end +$var reg 1 . bit $end +$var reg 16 / first_half_duration [15:0] $end +$var reg 16 0 second_half_duration [15:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx 0 +bx / +x. +x- +b0 , +b0 + +x* +b0 ) +b0 ( +b0 ' +b0 & +0% +0$ +0# +0" +0! +$end +#1 +0* +1# +#2 +0# +#3 +1# +#4 +0# +#5 +1# +#6 +0# +#7 +1# +#8 +0# +#9 +1# +#10 +0# +#11 +1# +#12 +0# +#13 +1# +#14 +0# +#15 +1# +#16 +0# +#17 +1# +#18 +0# +#19 +1# +#20 +0# +#21 +1# +#22 +0# +#23 +1# +#24 +0# +#25 +1# +#26 +0# +#27 +1# +#28 +0# +#29 +1# +#30 +0# +#31 +1# +#32 +0# +1- +#33 +1# +#34 +0# +#35 +1# +#36 +0# +#37 +1# +#38 +0# +#39 +1# +#40 +0# +b1 ( +b100 ' +1% +#41 +b101 ' +1! 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