From d3ca7a1d450551961ec83124971b801528f03c9d Mon Sep 17 00:00:00 2001 From: Andrew Kay Date: Sun, 21 Jun 2020 18:06:14 -0500 Subject: [PATCH] testing rx_coax_bit_timer on TinyFPGA --- interface2/firmware/.gitignore | 1 + interface2/firmware/platformio.ini | 6 + interface2/firmware/src/main.cpp | 59 ++++ interface2/rtl/coax_rx_bit_timer.v | 2 +- interface2/rtl/pins.pcf | 42 +-- interface2/rtl/top.v | 3 + interface2/tests/coax_rx_bit_timer_tb.v | 8 +- .../tests/coax_rx_bit_timer_tb.vcd_snapshot | 304 +++++++++--------- 8 files changed, 246 insertions(+), 179 deletions(-) create mode 100644 interface2/firmware/.gitignore create mode 100644 interface2/firmware/platformio.ini create mode 100644 interface2/firmware/src/main.cpp diff --git a/interface2/firmware/.gitignore b/interface2/firmware/.gitignore new file mode 100644 index 0000000..03f4a3c --- /dev/null +++ b/interface2/firmware/.gitignore @@ -0,0 +1 @@ +.pio diff --git a/interface2/firmware/platformio.ini b/interface2/firmware/platformio.ini new file mode 100644 index 0000000..e5a9eca --- /dev/null +++ b/interface2/firmware/platformio.ini @@ -0,0 +1,6 @@ +[env] +framework = arduino + +[env:teensy40] +platform = teensy +board = teensy40 diff --git a/interface2/firmware/src/main.cpp b/interface2/firmware/src/main.cpp new file mode 100644 index 0000000..5e75b01 --- /dev/null +++ b/interface2/firmware/src/main.cpp @@ -0,0 +1,59 @@ +#include + +#define RESET_PIN 2 // FPGA #9 + +char buffer[20 + 1]; +int bufferIndex = 0; + +void doReset() +{ + Serial.println("RESET"); + + digitalWrite(RESET_PIN, HIGH); + digitalWrite(RESET_PIN, LOW); + + Serial.println("OK"); +} + +void setup() +{ + pinMode(RESET_PIN, OUTPUT); + + digitalWrite(RESET_PIN, LOW); + + Serial.begin(115200); + + while (Serial.available() > 0) { + Serial.read(); + } + + Serial.println("OK"); +} + +void loop() +{ + if (Serial.available() > 0) { + uint8_t byte = Serial.read(); + + if (byte == '\r') { + buffer[bufferIndex] = 0; + + Serial.println(); + + if (strncmp(buffer, "reset", 20) == 0) { + doReset(); + } else { + Serial.println("UNRECOGNIZED COMMAND"); + } + + Serial.flush(); + + bufferIndex = 0; + } else { + buffer[bufferIndex++] = byte; + } + + Serial.write(byte); + Serial.flush(); + } +} diff --git a/interface2/rtl/coax_rx_bit_timer.v b/interface2/rtl/coax_rx_bit_timer.v index c6a4291..2d9e8f0 100644 --- a/interface2/rtl/coax_rx_bit_timer.v +++ b/interface2/rtl/coax_rx_bit_timer.v @@ -1,6 +1,6 @@ `default_nettype none -module coax_rx_bit_timer( +module coax_rx_bit_timer ( input clk, input rx, input reset, diff --git a/interface2/rtl/pins.pcf b/interface2/rtl/pins.pcf index 96cf71b..bd03a8f 100644 --- a/interface2/rtl/pins.pcf +++ b/interface2/rtl/pins.pcf @@ -2,32 +2,36 @@ set_io --warn-no-port clk_16mhz B2 # Transmitter -set_io --warn-no-port tx_active A2 # 1 -set_io --warn-no-port tx_inverted A1 # 2 -set_io --warn-no-port tx_delay B1 # 3 +#set_io --warn-no-port tx_active A2 # 1 +#set_io --warn-no-port tx_inverted A1 # 2 +#set_io --warn-no-port tx_delay B1 # 3 -set_io --warn-no-port tx_load D2 # 6 -set_io --warn-no-port tx_full D1 # 7 +#set_io --warn-no-port tx_load D2 # 6 +#set_io --warn-no-port tx_full D1 # 7 # Receiver set_io --warn-no-port rx C2 # 4 -set_io --warn-no-port rx_enable E1 # 9 -set_io --warn-no-port rx_active G2 # 10 -set_io --warn-no-port rx_data_available H1 # 11 -set_io --warn-no-port rx_data_read J1 # 12 +set_io --warn-no-port reset E1 # 9 +set_io --warn-no-port sample G2 # 10 +set_io --warn-no-port synchronized H1 # 11 + +#set_io --warn-no-port rx_enable E1 # 9 +#set_io --warn-no-port rx_active G2 # 10 +#set_io --warn-no-port rx_data_available H1 # 11 +#set_io --warn-no-port rx_data_read J1 # 12 # Shared data bus -set_io --warn-no-port data[9] B6 # 23 -set_io --warn-no-port data[8] A7 -set_io --warn-no-port data[7] B7 -set_io --warn-no-port data[6] A8 -set_io --warn-no-port data[5] B8 -set_io --warn-no-port data[4] A9 -set_io --warn-no-port data[3] C9 -set_io --warn-no-port data[2] D8 -set_io --warn-no-port data[1] D9 -set_io --warn-no-port data[0] H9 # 14 +#set_io --warn-no-port data[9] B6 # 23 +#set_io --warn-no-port data[8] A7 +#set_io --warn-no-port data[7] B7 +#set_io --warn-no-port data[6] A8 +#set_io --warn-no-port data[5] B8 +#set_io --warn-no-port data[4] A9 +#set_io --warn-no-port data[3] C9 +#set_io --warn-no-port data[2] D8 +#set_io --warn-no-port data[1] D9 +#set_io --warn-no-port data[0] H9 # 14 set_io --warn-no-port debug H2 # 13 diff --git a/interface2/rtl/top.v b/interface2/rtl/top.v index 56c93cd..a0df9b9 100644 --- a/interface2/rtl/top.v +++ b/interface2/rtl/top.v @@ -9,6 +9,7 @@ module top ( input reset, output sample, output synchronized, + output debug, output usb_pu ); @@ -49,5 +50,7 @@ module top ( .synchronized(synchronized) ); + assign debug = rx_1; + assign usb_pu = 0; endmodule diff --git a/interface2/tests/coax_rx_bit_timer_tb.v b/interface2/tests/coax_rx_bit_timer_tb.v index b1e90dd..36bb6cb 100644 --- a/interface2/tests/coax_rx_bit_timer_tb.v +++ b/interface2/tests/coax_rx_bit_timer_tb.v @@ -1,6 +1,6 @@ `default_nettype none -module coax_rx_bit_timer_tb(); +module coax_rx_bit_timer_tb (); reg clk = 0; initial begin @@ -61,11 +61,7 @@ module coax_rx_bit_timer_tb(); input bit ); begin - rx = !bit; - #8; - rx = bit; - #8; - rx = 0; + rx_bit_custom(bit, 8, 8); end endtask diff --git a/interface2/tests/coax_rx_bit_timer_tb.vcd_snapshot b/interface2/tests/coax_rx_bit_timer_tb.vcd_snapshot index bce01dc..88bf912 100644 --- a/interface2/tests/coax_rx_bit_timer_tb.vcd_snapshot +++ b/interface2/tests/coax_rx_bit_timer_tb.vcd_snapshot @@ -1,5 +1,5 @@ $date - Mon Jun 15 21:59:45 2020 + Sun Jun 21 18:50:14 2020 $end $version Icarus Verilog @@ -121,6 +121,9 @@ $end 1# #32 0# +b1000 0 +b1000 / +1. 1- #33 1# @@ -183,6 +186,7 @@ b11 , b1000 ' b100 ) 1! +0. 0- 1% #49 @@ -264,6 +268,7 @@ b11 , 1# #64 0# +1. 1- #65 b0 ' @@ -347,7 +352,6 @@ b11 , b1000 ' b100 ) 1! -b1000 0 b1001 / 0. 1% @@ -429,11 +433,11 @@ b11 , 0# #97 1* -b100 & -b0 , +b1000 & +b100 , 1# -b101 ' -b1 ) +b0 ' +b101 ) 1! 1% b111 0 @@ -441,15 +445,44 @@ b110 / #98 0# #99 +b1 ' +b110 ) +1! +b0 & +b101 , +1# +#100 +0# +#101 +b10 ' +b111 ) +1! +b1 & +b110 , +1# +#102 +0# +#103 +0* +b100 & +b0 , +1# +b101 ' +b1 ) +1! +0% +#104 +0# +#105 b110 ' b10 ) 1! b101 & b1 , 1# -#100 +#106 0# -#101 +#107 1" b111 ' b11 ) @@ -457,44 +490,15 @@ b11 ) b110 & b10 , 1# -#102 +#108 0# -#103 -0* -b111 & -b11 , -1# +#109 b1000 ' b100 ) 1! 0" -0% -#104 -0# -#105 -b0 ' -b101 ) -1! -b1000 & -b100 , -1# -#106 -0# -#107 -b1 ' -b110 ) -1! -b0 & -b101 , -1# -#108 -0# -#109 -b10 ' -b111 ) -1! -b1 & -b110 , +b111 & +b11 , 1# #110 0# @@ -502,133 +506,141 @@ b1000 0 b11000 / 1. #111 +b0 ' +b101 ) +1! +b1000 & +b100 , +1# +#112 +0# +#113 +b1 ' +b110 ) +1! +b0 & +b101 , +1# +#114 +0# +#115 +b10 ' +b111 ) +1! +b1 & +b110 , +1# +#116 +0# +#117 b11 ' b1000 ) 1! b10 & b111 , 1# -#112 +#118 0# -#113 +#119 b100 ' b1001 ) 1! b11 & b1000 , 1# -#114 +#120 0# -#115 +#121 b101 ' b1010 ) 1! b100 & b1001 , 1# -#116 +#122 0# -#117 +#123 b110 ' b10 ( 1! b101 & b1010 , 1# -#118 +#124 0# -#119 +#125 1" b111 ' 0! b110 & b10 + 1# -#120 -0# -#121 -b1000 ' -0" -b111 & -1# -#122 -0# -#123 -b0 ' -b1000 & -1# -#124 -0# -#125 -b1 ' -b0 & -1# #126 0# #127 -b10 ' -b1 & +b1000 ' +0" +b111 & 1# #128 0# #129 -b11 ' -b10 & +b0 ' +b1000 & 1# #130 0# #131 -b100 ' -b11 & +b1 ' +b0 & 1# #132 0# #133 -b101 ' -b100 & +b10 ' +b1 & 1# #134 0# -b101 ' +b10 ' 1% #135 -b110 ' +b11 ' 1* -b101 & +b10 & 1# #136 0# #137 -1" -b111 ' -b110 & +b100 ' +b11 & 1# #138 0# #139 -b1000 ' -0" -b111 & +b101 ' +b100 & 1# #140 0# #141 -b0 ' -b1000 & +b110 ' +b101 & 1# #142 0# -b0 ' +b110 ' 1$ 0% #143 b0 ( 0* b0 + -b0 & +b110 & 1# #144 0# +b1000 / 0$ #145 1# @@ -690,143 +702,129 @@ b11 , 1# #160 0# -b100 ' -b0 ) +b1000 ' +b100 ) 1! 0% #161 -b101 ' -b1 ) +b0 ' +b101 ) 1! 0* -b100 & -b0 , +b1000 & +b100 , 1# #162 0# #163 -b110 ' -b10 ) -1! -b101 & -b1 , -1# -#164 -0# -#165 -1" -b111 ' -b11 ) -1! -b110 & -b10 , -1# -#166 -0# -#167 -b1000 ' -b100 ) -1! -0" -b111 & -b11 , -1# -#168 -0# -#169 -b0 ' -b101 ) -1! -b1000 & -b100 , -1# -#170 -0# -#171 b1 ' b110 ) 1! b0 & b101 , 1# -#172 +#164 0# -#173 +#165 b10 ' b111 ) 1! b1 & b110 , 1# -#174 +#166 0# -#175 +#167 b11 ' b1000 ) 1! b10 & b111 , 1# -#176 +#168 0# -#177 +#169 b100 ' b1001 ) 1! b11 & b1000 , 1# -#178 +#170 0# -#179 +#171 b101 ' b1010 ) 1! b100 & b1001 , 1# -#180 +#172 0# -#181 +#173 b110 ' b10 ( 1! b101 & b1010 , 1# -#182 +#174 0# -#183 +#175 1" b111 ' 0! b110 & b10 + 1# -#184 +#176 0# -#185 +#177 b1000 ' 0" b111 & 1# +#178 +0# +#179 +b0 ' +b1000 & +1# +#180 +0# +#181 +b1 ' +b0 & +1# +#182 +0# +#183 +b10 ' +b1 & +1# +#184 +0# +#185 +b11 ' +b10 & +1# #186 0# #187 -b0 ' -b1000 & +b100 ' +b11 & 1# #188 0# #189 -b1 ' -b0 & +b101 ' +b100 & 1# #190 0# #191 -b10 ' -b1 & +b110 ' +b101 & 1# #192 0#