From eacb8f0eea65f451433abb7cce09063434e13806 Mon Sep 17 00:00:00 2001
From: Andrew Kay <git@ajk.me>
Date: Sun, 5 Jul 2020 14:41:33 -0500
Subject: [PATCH] Work in progress

---
 interface2/rtl/coax_rx.v      | 52 +++++++++++++++++++-----
 interface2/tests/coax_rx_tb.v | 75 ++++++++++++++++++++++++++++++++++-
 2 files changed, 117 insertions(+), 10 deletions(-)

diff --git a/interface2/rtl/coax_rx.v b/interface2/rtl/coax_rx.v
index 5e1fc65..62852a0 100644
--- a/interface2/rtl/coax_rx.v
+++ b/interface2/rtl/coax_rx.v
@@ -11,7 +11,8 @@ module coax_rx (
     parameter CLOCKS_PER_BIT = 8;
 
     localparam LOSS_OF_MID_BIT_TRANSITION_ERROR = 10'b0000000001;
-    localparam PARITY_ERROR                     = 10'b0000000010;
+    localparam PARITY_ERROR = 10'b0000000010;
+    localparam INVALID_END_SEQUENCE_ERROR = 10'b0000000100;
 
     localparam IDLE = 0;
     localparam START_SEQUENCE_1 = 1;
@@ -26,14 +27,15 @@ module coax_rx (
     localparam SYNC_BIT = 10;
     localparam DATA_BIT = 11;
     localparam PARITY_BIT = 12;
-    localparam ERROR = 50;
+    localparam END_SEQUENCE_1 = 13;
+    localparam END_SEQUENCE_2 = 14;
+    localparam ERROR = 15;
 
-    // TODO: size...
-    reg [8:0] state = IDLE;
-    reg [8:0] next_state;
-    reg [8:0] previous_state;
-    reg [8:0] state_counter;
-    reg [8:0] next_state_counter;
+    reg [3:0] state = IDLE;
+    reg [3:0] next_state;
+    reg [3:0] previous_state;
+    reg [3:0] state_counter;
+    reg [3:0] next_state_counter;
 
     reg previous_rx;
 
@@ -181,9 +183,14 @@ module coax_rx (
                 if (sample && synchronized)
                 begin
                     if (rx)
+                    begin
+                        next_bit_counter = 0;
                         next_state = DATA_BIT;
+                    end
                     else
+                    begin
                         next_state = IDLE;
+                    end
                 end
                 else if (state_counter >= CLOCKS_PER_BIT)
                 begin
@@ -197,7 +204,15 @@ module coax_rx (
                begin
                    if (synchronized)
                    begin
-                       // ...
+                       if (rx)
+                       begin
+                           next_bit_counter = 0;
+                           next_state = DATA_BIT;
+                       end
+                       else
+                       begin
+                           next_state = END_SEQUENCE_1;
+                       end
                    end
                    else
                    begin
@@ -256,6 +271,25 @@ module coax_rx (
                    end
                end
            end
+
+           END_SEQUENCE_1:
+           begin
+               if (rx)
+               begin
+                   next_state = END_SEQUENCE_2;
+               end
+               else if (state_counter >= CLOCKS_PER_BIT)
+               begin
+                   next_data = INVALID_END_SEQUENCE_ERROR;
+                   next_state = ERROR;
+               end
+           end
+
+           END_SEQUENCE_2:
+           begin
+               // TODO: Let's do more!
+               next_state = IDLE;
+           end
         endcase
     end
 
diff --git a/interface2/tests/coax_rx_tb.v b/interface2/tests/coax_rx_tb.v
index fed01da..cabe7f4 100644
--- a/interface2/tests/coax_rx_tb.v
+++ b/interface2/tests/coax_rx_tb.v
@@ -40,8 +40,10 @@ module coax_rx_tb;
         test_11;
         test_12;
         test_13;
-        */
         test_14;
+        test_15;
+        */
+        test_16;
 
         $finish;
     end
@@ -377,6 +379,77 @@ module coax_rx_tb;
     end
     endtask
 
+    task test_15;
+    begin
+        $display("START: test_15");
+
+        `assert_equal(dut.state, dut.IDLE, "state should be IDLE");
+
+        rx_start_sequence;
+        rx_bit(1); // SYNC_BIT
+        rx_bit(0); // MSB DATA_BIT
+        rx_bit(1);
+        rx_bit(1);
+        rx_bit(0);
+        rx_bit(1);
+        rx_bit(1);
+        rx_bit(0);
+        rx_bit(0);
+        rx_bit(1);
+        rx_bit(1); // LSB DATA_BIT
+        rx_bit(1); // PARITY_BIT
+        rx_bit(0);
+
+        #64;
+
+        `assert_equal(dut.state, dut.ERROR, "State should be ERROR");
+
+        `assert_high(dut.error, "error should be HIGH");
+        `assert_equal(dut.data, dut.INVALID_END_SEQUENCE_ERROR, "data should be INVALID_END_SEQUENCE_ERROR");
+
+        dut_reset;
+
+        #16;
+
+        `assert_equal(dut.state, dut.IDLE, "state should be IDLE");
+
+        $display("END: test_15");
+    end
+    endtask
+
+    task test_16;
+    begin
+        $display("START: test_16");
+
+        `assert_equal(dut.state, dut.IDLE, "state should be IDLE");
+
+        rx_start_sequence;
+        rx_bit(1); // SYNC_BIT
+        rx_bit(0); // MSB DATA_BIT
+        rx_bit(1);
+        rx_bit(1);
+        rx_bit(0);
+        rx_bit(1);
+        rx_bit(1);
+        rx_bit(0);
+        rx_bit(0);
+        rx_bit(1);
+        rx_bit(1); // LSB DATA_BIT
+        rx_bit(1); // PARITY_BIT
+        rx_bit(0);
+        
+        rx = 1;
+        #16;
+        rx = 0;
+
+        #64;
+
+        `assert_equal(dut.state, dut.IDLE, "state should be IDLE");
+
+        $display("END: test_16");
+    end
+    endtask
+
     task dut_reset;
     begin
         reset = 1;