$date
	Sun Jun 21 18:50:14 2020
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module coax_rx_bit_timer_tb $end
$var wire 1 ! synchronized $end
$var wire 1 " sample $end
$var reg 1 # clk $end
$var reg 1 $ reset $end
$var reg 1 % rx $end
$scope module dut $end
$var wire 1 # clk $end
$var wire 1 $ reset $end
$var wire 1 % rx $end
$var reg 4 & bit_counter [3:0] $end
$var reg 4 ' next_bit_counter [3:0] $end
$var reg 2 ( next_state [1:0] $end
$var reg 5 ) next_transition_counter [4:0] $end
$var reg 1 * previous_rx $end
$var reg 1 " sample $end
$var reg 2 + state [1:0] $end
$var reg 1 ! synchronized $end
$var reg 5 , transition_counter [4:0] $end
$upscope $end
$scope task rx_bit $end
$var reg 1 - bit $end
$upscope $end
$scope task rx_bit_custom $end
$var reg 1 . bit $end
$var reg 16 / first_half_duration [15:0] $end
$var reg 16 0 second_half_duration [15:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx 0
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0!
$end
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0#