#-- Synopsys, Inc.
#-- Project file /home/andrew/lattice_coax/coax/coax_syn.prj
#project files

add_file -verilog -lib work "coax_buffered_rx.v"
add_file -verilog -lib work "coax_rx.v"
add_file -verilog -lib work "coax_rx_bit_timer.v"
add_file -verilog -lib work "coax_tx.v"
add_file -verilog -lib work "coax_tx_bit_timer.v"
add_file -verilog -lib work "coax_tx_distorter.v"
add_file -verilog -lib work "control.v"
add_file -verilog -lib work "spi_device.v"
add_file -verilog -lib work "coax_buffered_tx.v"
add_file -verilog -lib work "coax_buffer.v"
add_file -verilog -lib work "third_party/fifo_sync_ram.v"
add_file -verilog -lib work "third_party/ram_sdp.v"
add_file -verilog -lib work "strobe_cdc.v"
add_file -verilog -lib work "top.v"
add_file -verilog -lib work "dual_clock_spi_device.v"
add_file -constraint -lib work "clocks.sdc"
#implementation: "coax_Implmnt"
impl -add coax_Implmnt -type fpga

#implementation attributes
set_option -vlog_std v2001
set_option -project_relative_includes 1

#device options
set_option -technology SBTiCE40UP
set_option -part iCE40UP5K
set_option -package SG48
set_option -speed_grade
set_option -part_companion ""

#compilation/mapping options

# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 0

# Silicon Blue iCE40UP
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 2
set_option -fixgeneratedclocks 0

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"
project -result_file ./coax_Implmnt/coax.edf
project -log_file "./coax_Implmnt/coax.srr"
impl -active coax_Implmnt
project -run synthesis -clean