mirror of
https://github.com/lowobservable/coax.git
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57 lines
1.6 KiB
Verilog
57 lines
1.6 KiB
Verilog
// Copyright (c) 2021, Andrew Kay
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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//
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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`default_nettype none
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module coax_rx_blanker (
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input clk,
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input reset,
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input enable,
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input rx_input,
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input tx_active,
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output reg rx_output
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);
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parameter DELAY_CLOCKS = 2;
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reg rx_input_d0;
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always @(posedge clk)
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begin
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rx_input_d0 <= rx_input;
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end
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reg [DELAY_CLOCKS-1:0] blank;
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always @(posedge clk)
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begin
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if (reset)
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blank <= { (DELAY_CLOCKS){1'b0} };
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else if (tx_active)
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blank <= { (DELAY_CLOCKS){1'b1} };
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else
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blank <= { blank[DELAY_CLOCKS-2:0], 1'b0 };
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end
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always @(posedge clk)
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begin
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// TODO: should enable be delayed 1 clock to match input?
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if (!enable || !blank[DELAY_CLOCKS-1])
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rx_output <= rx_input_d0;
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else
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rx_output <= 1'b0;
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end
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endmodule
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