mirror of
https://github.com/lowobservable/coax.git
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72 lines
2.0 KiB
Verilog
72 lines
2.0 KiB
Verilog
// Copyright (c) 2021, Andrew Kay
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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//
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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`default_nettype none
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module coax_tx_rx_frontend (
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input clk,
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input reset,
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input loopback,
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input tx_active_input,
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input tx_input,
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output rx_output,
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// The outside world...
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output tx_active_output,
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output tx_output,
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output tx_n_output,
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output tx_delay_output,
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input rx_input,
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output rx_debug
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);
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parameter CLOCKS_PER_BIT = 8;
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coax_tx_distorter #(
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.CLOCKS_PER_BIT(CLOCKS_PER_BIT)
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) coax_tx_distorter (
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.clk(clk),
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.active_input(!loopback && tx_active_input),
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.tx_input(tx_input),
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.active_output(tx_active_output),
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.tx_output(tx_output),
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.tx_delay_output(tx_delay_output),
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.tx_n_output(tx_n_output)
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);
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reg [1:0] rx_input_d;
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reg internal_rx;
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always @(posedge clk)
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begin
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rx_input_d <= { rx_input_d[0], rx_input };
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internal_rx <= loopback ? tx_input : rx_input_d[1];
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end
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coax_rx_blanker #(
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.DELAY_CLOCKS(2 + 4) // To account for the RX input 2FF synchronizer and more
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) coax_rx_blanker (
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.clk(clk),
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.reset(reset),
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.enable(!loopback),
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.rx_input(internal_rx),
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.tx_active(tx_active_output),
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.rx_output(rx_output)
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);
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assign rx_debug = internal_rx;
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endmodule
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