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23 lines
435 B
Verilog
23 lines
435 B
Verilog
`default_nettype none
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module coax_tx (
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input clk,
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output tx
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);
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parameter CLOCKS_PER_BIT = 8;
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reg [$clog2(CLOCKS_PER_BIT):0] bit_counter = 0;
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reg bit = 1'b1;
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always @(posedge clk)
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begin
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if (bit_counter == CLOCKS_PER_BIT - 1)
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bit_counter <= 0;
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else
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bit_counter <= bit_counter + 1;
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end
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assign tx = bit_counter < (CLOCKS_PER_BIT / 2) ? ~bit : bit;
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endmodule
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