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34 lines
706 B
Verilog
34 lines
706 B
Verilog
`default_nettype none
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module coax_tx_bit_timer (
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input clk,
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input reset,
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output first_half,
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output second_half,
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output end_strobe
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);
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parameter CLOCKS_PER_BIT = 8;
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reg [$clog2(CLOCKS_PER_BIT):0] counter = 0;
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always @(posedge clk or posedge reset)
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begin
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if (reset)
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begin
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counter <= 0;
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end
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else
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begin
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if (counter == CLOCKS_PER_BIT - 1)
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counter <= 0;
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else
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counter <= counter + 1;
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end
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end
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assign first_half = (counter < CLOCKS_PER_BIT / 2);
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assign second_half = ~first_half;
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assign end_strobe = (counter == CLOCKS_PER_BIT - 1);
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endmodule
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