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43 lines
1.2 KiB
Verilog
43 lines
1.2 KiB
Verilog
// Copyright (c) 2020, Andrew Kay
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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//
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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`default_nettype none
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module strobe_cdc (
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input clk_in,
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input strobe_in,
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input clk_out,
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output reg strobe_out
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);
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reg toggle_in;
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always @(posedge clk_in)
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begin
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if (strobe_in)
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toggle_in <= ~toggle_in;
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end
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reg [2:0] toggle_out;
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always @(posedge clk_out)
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begin
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toggle_out <= { toggle_out[1:0], toggle_in };
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strobe_out <= 0;
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if (toggle_out[2] != toggle_out[1])
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strobe_out <= 1;
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end
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endmodule
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