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81 lines
1.5 KiB
Verilog
81 lines
1.5 KiB
Verilog
`default_nettype none
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module top (
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input clk_16mhz,
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// Transmitter
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input tx_load,
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output tx_full,
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output tx_active,
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output tx_delay,
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output tx_inverted,
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// Receiver
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input rx_enable,
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input rx,
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output rx_active,
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output rx_data_available,
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input rx_data_read,
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// Shared data bus
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inout [9:0] data,
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output debug,
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output usb_pu
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);
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// 19 MHz
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//
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// icepll -i 16 -o 18.869
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wire clk_19mhz;
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000),
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.DIVF(7'b0100101),
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.DIVQ(3'b101),
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.FILTER_RANGE(3'b001)
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) clk_19mhz_pll (
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(clk_16mhz),
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.PLLOUTCORE(clk_19mhz)
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);
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wire [9:0] tx_data;
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assign tx_data = data;
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coax_tx #(
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.CLOCKS_PER_BIT(8)
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) coax_tx (
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.clk(clk_19mhz),
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.load(tx_load),
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.data(tx_data),
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.full(tx_full),
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.active(tx_active),
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.tx_delay(tx_delay),
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.tx_inverted(tx_inverted)
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);
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wire [9:0] rx_data;
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coax_rx #(
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.CLOCKS_PER_BIT(8)
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) coax_rx (
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.clk(clk_19mhz),
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.rx(rx),
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.enable(rx_enable && !tx_active),
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.active(rx_active),
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.data(rx_data),
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.data_available(rx_data_available),
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.data_read(rx_data_read)
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);
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assign data = rx_enable ? rx_data : 10'bzzzzzzzzzz;
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assign debug = rx;
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assign usb_pu = 0;
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endmodule
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