mirror of
https://github.com/lowobservable/coax.git
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111 lines
2.7 KiB
Verilog
111 lines
2.7 KiB
Verilog
`default_nettype none
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module hello_world (
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input clk,
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output tx_active,
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output tx,
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output tx_delay,
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output tx_inverted
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);
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wire load;
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reg [9:0] data;
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wire full;
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coax_tx coax_tx (
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.clk(clk),
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.load(load),
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.data(data),
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.full(full),
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.active(tx_active),
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.tx(tx),
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.tx_delay(tx_delay),
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.tx_inverted(tx_inverted)
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);
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localparam IDLE = 0;
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localparam WORD_1 = 1;
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localparam WORD_2 = 2;
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localparam WORD_3 = 3;
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localparam WORD_4 = 4;
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localparam WORD_5 = 5;
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localparam WORD_6 = 6;
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localparam WORD_7 = 7;
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localparam WORD_8 = 8;
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localparam WORD_9 = 9;
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localparam WORD_10 = 10;
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localparam WORD_11 = 11;
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localparam WORD_12 = 12;
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reg [4:0] state = IDLE;
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reg [4:0] next_state;
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reg [4:0] previous_state;
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always @(*)
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begin
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next_state <= state;
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case (state)
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WORD_1: next_state <= WORD_2;
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WORD_2: next_state <= WORD_3;
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WORD_3: next_state <= WORD_4;
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WORD_4: next_state <= WORD_5;
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WORD_5: next_state <= WORD_6;
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WORD_6: next_state <= WORD_7;
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WORD_7: next_state <= WORD_8;
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WORD_8: next_state <= WORD_9;
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WORD_9: next_state <= WORD_10;
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WORD_10: next_state <= WORD_11;
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WORD_11: next_state <= WORD_12;
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WORD_12: next_state <= IDLE;
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endcase
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end
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reg [23:0] counter = 0;
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reg [8:0] state_counter = 0;
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always @(posedge clk)
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begin
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previous_state <= state;
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if (counter == 50)
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begin
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state <= WORD_1;
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state_counter <= 0;
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end
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else if (state > IDLE)
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begin
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if (state_counter > 32 && !full)
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begin
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state <= next_state;
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state_counter <= 0;
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end
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else
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state_counter <= state_counter + 1;
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end
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counter <= counter + 1;
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end
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always @(*)
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begin
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data <= 10'b0000000000;
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case (state)
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WORD_1: data <= 10'b0000110001; // WRITE_DATA
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WORD_2: data <= 10'b1010011100; // H
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WORD_3: data <= 10'b1000010010; // e
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WORD_4: data <= 10'b1000101110; // l
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WORD_5: data <= 10'b1000101110; // l
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WORD_6: data <= 10'b1000111010; // o
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WORD_7: data <= 10'b0000000010; // <space>
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WORD_8: data <= 10'b1001011010; // w
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WORD_9: data <= 10'b1000111010; // o
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WORD_10: data <= 10'b1001000100; // r
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WORD_11: data <= 10'b1000101110; // l
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WORD_12: data <= 10'b1000001100; // d
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endcase
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end
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assign load = state != IDLE && state_counter < 8;
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endmodule
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