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https://github.com/lowobservable/coax.git
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71 lines
1.1 KiB
Verilog
71 lines
1.1 KiB
Verilog
`default_nettype none
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module coax_rx_tb();
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reg clk = 0;
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initial
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begin
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forever
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begin
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#1 clk <= ~clk;
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end
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end
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reg tx_load = 0;
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reg [9:0] tx_data;
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wire tx_tx;
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coax_tx #(
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.CLOCKS_PER_BIT(8)
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) tx (
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.clk(clk),
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.load(tx_load),
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.data(tx_data),
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.tx(tx_tx)
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);
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reg rx_data_read = 0;
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wire rx_data_available;
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coax_rx #(
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.CLOCKS_PER_BIT(8)
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) dut (
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.clk(clk),
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.rx(tx_tx),
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.data_read(rx_data_read),
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.data_available(rx_data_available)
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);
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initial
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begin
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$dumpfile("coax_rx_tb.vcd");
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$dumpvars(0, coax_rx_tb);
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#8
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tx_data = 10'b0000000101;
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tx_load = 1;
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#2 tx_load = 0;
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#32
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tx_data = 10'b1111111111;
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tx_load = 1;
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#2 tx_load = 0;
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repeat(200) @(posedge clk);
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rx_data_read = 1;
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#4 rx_data_read = 0;
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repeat(100) @(posedge clk);
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rx_data_read = 1;
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#4 rx_data_read = 0;
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repeat(100) @(posedge clk);
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$finish;
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end
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endmodule
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