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53 lines
992 B
Verilog
53 lines
992 B
Verilog
`default_nettype none
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module top (
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input clk_16mhz,
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output tx_active,
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output tx,
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output tx_delay,
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output tx_inverted,
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output usb_pu
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);
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// 19 MHz
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//
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// icepll -i 16 -o 18.869
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wire clk_19mhz;
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000),
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.DIVF(7'b0100101),
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.DIVQ(3'b101),
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.FILTER_RANGE(3'b001)
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) clk_19mhz_pll (
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(clk_16mhz),
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.PLLOUTCORE(clk_19mhz)
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);
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wire load;
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reg [9:0] data = 10'b0000000101;
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coax_tx coax_tx (
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.clk(clk_19mhz),
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.load(load),
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.data(data),
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.active(tx_active),
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.tx(tx),
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.tx_delay(tx_delay),
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.tx_inverted(tx_inverted)
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);
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assign load = (counter == 16'b1111_1111_1111_1111);
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reg [15:0] counter = 0;
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always @(posedge clk_19mhz)
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begin
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counter <= counter + 1;
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end
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assign usb_pu = 0;
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endmodule
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