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33 lines
472 B
Verilog
33 lines
472 B
Verilog
`default_nettype none
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module hello_world_tb();
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reg clk = 0;
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initial
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begin
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forever
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begin
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#1 clk <= ~clk;
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end
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end
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wire tx;
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wire tx_active;
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hello_world dut (
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.clk(clk),
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.tx(tx),
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.tx_active(tx_active)
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);
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initial
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begin
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$dumpfile("hello_world_tb.vcd");
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$dumpvars(0, hello_world_tb);
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repeat(2000) @(posedge clk);
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$finish;
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end
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endmodule
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