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75 lines
1.3 KiB
Verilog
75 lines
1.3 KiB
Verilog
`default_nettype none
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module top (
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input clk_16mhz,
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// Receiver
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input rx,
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output rx_active,
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output rx_error,
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output rx_data_available,
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input rx_read,
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// Shared data bus
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inout [9:0] data,
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input reset,
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output debug,
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output usb_pu
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);
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// 38 MHz
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//
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// icepll -i 16 -o 37.738
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wire clk_38mhz;
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000),
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.DIVF(7'b0100101),
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.DIVQ(3'b100),
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.FILTER_RANGE(3'b001)
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) clk_38mhz_pll (
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(clk_16mhz),
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.PLLOUTCORE(clk_38mhz)
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);
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reg rx_0 = 0;
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reg rx_1 = 0;
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reg rx_read_0 = 0;
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reg rx_read_1 = 0;
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always @(posedge clk_38mhz)
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begin
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rx_0 <= rx;
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rx_1 <= rx_0;
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rx_read_0 <= rx_read;
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rx_read_1 <= rx_read_0;
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end
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wire [9:0] rx_data;
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coax_rx #(
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.CLOCKS_PER_BIT(16)
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) coax_rx (
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.clk(clk_38mhz),
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.rx(rx_1),
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.reset(reset),
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.active(rx_active),
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.error(rx_error),
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.data(rx_data),
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.data_available(rx_data_available),
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.read(rx_read_1)
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);
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assign data = rx_data;
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assign debug = rx_1;
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assign usb_pu = 0;
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endmodule
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