From 22ae9e1dc6b9d00188d36fbfc8199f8e89e7d5a6 Mon Sep 17 00:00:00 2001
From: Mikael Pettersson <mikpelinux@gmail.com>
Date: Thu, 23 Jul 2020 21:55:07 +0200
Subject: [PATCH] sim: sim_boolean: handle ANDCM, add unit test

---
 erlang/apps/sim/src/sim_boolean.erl        | 17 +++++++++++++++++
 erlang/apps/sim/src/sim_core.erl           |  1 +
 erlang/apps/sim/test/sim_boolean_tests.erl | 14 ++++++++++++++
 3 files changed, 32 insertions(+)

diff --git a/erlang/apps/sim/src/sim_boolean.erl b/erlang/apps/sim/src/sim_boolean.erl
index b77c8cc..207dae0 100644
--- a/erlang/apps/sim/src/sim_boolean.erl
+++ b/erlang/apps/sim/src/sim_boolean.erl
@@ -30,6 +30,7 @@
         , handle_ANDCAB/4
         , handle_ANDCAI/4
         , handle_ANDCAM/4
+        , handle_ANDCM/4
         , handle_ANDI/4
         , handle_ANDM/4
         , handle_SETMB/4
@@ -233,6 +234,22 @@ handle_SETMB(Core, Mem, IR, EA) ->
                           fun(Core1, Mem1) -> handle_SETMB(Core1, Mem1, IR, EA) end)
   end.
 
+%% ANDCM - And Complement of Memory with AC
+
+-spec handle_ANDCM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
+      -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
+handle_ANDCM(Core, Mem, IR, EA) ->
+  case sim_core:c(Core, Mem, EA) of
+    {ok, CE} ->
+      AC = IR band 8#17,
+      CA = sim_core:get_ac(Core, AC),
+      Word = CA band bnot CE,
+      sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
+    {error, Reason} ->
+      sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
+                          fun(Core1, Mem1) -> handle_ANDCM(Core1, Mem1, IR, EA) end)
+  end.
+
 %% Miscellaneous ===============================================================
 
 ea_address(#ea{section = Section, offset = Offset}) ->
diff --git a/erlang/apps/sim/src/sim_core.erl b/erlang/apps/sim/src/sim_core.erl
index cdecb64..2135e99 100644
--- a/erlang/apps/sim/src/sim_core.erl
+++ b/erlang/apps/sim/src/sim_core.erl
@@ -269,6 +269,7 @@ dispatch(Core, Mem, IR, EA) ->
     8#415 -> sim_boolean:handle_SETMI(Core, Mem, IR, EA); % SETMI = MOVEI in section 0, XMOVEI elsewhere
     8#416 -> sim_boolean:handle_SETMM(Core, Mem, IR, EA);
     8#417 -> sim_boolean:handle_SETMB(Core, Mem, IR, EA);
+    8#420 -> sim_boolean:handle_ANDCM(Core, Mem, IR, EA);
     _ ->
       PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
       {Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}
diff --git a/erlang/apps/sim/test/sim_boolean_tests.erl b/erlang/apps/sim/test/sim_boolean_tests.erl
index 1909979..526f3c3 100644
--- a/erlang/apps/sim/test/sim_boolean_tests.erl
+++ b/erlang/apps/sim/test/sim_boolean_tests.erl
@@ -60,6 +60,7 @@
 -define(OP_XMOVEI, ?OP_SETMI).
 -define(OP_SETMM, 8#416).
 -define(OP_SETMB, 8#417).
+-define(OP_ANDCM, 8#420).
 
 %% 2.4 Boolean Functions =======================================================
 
@@ -284,6 +285,19 @@ setmb_test() ->
          , {#ea{section = 1, offset = 0, islocal = false}, 8#42} % AC0 = 42
          ]).
 
+%% ANDCM - And Complement of Memory with AC
+
+andcm_test() ->
+  Prog =
+    [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 8#333333)} % 1,,100/ MOVEI 1,333333
+    , {1, 8#101, ?INSN(?OP_ANDCM, 1, 0, 0, 8#200)}    % 1,,101/ ANDCM 1,200
+    , {1, 8#102, ?INSN_INVALID}                       % 1,,102/ <invalid>
+    , {1, 8#200, ?COMMA2(0, 8#707070)}                % 1,,200/ 0,,707070
+    ],
+  expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
+         [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 8#030303)} % AC1 = 0,,030303
+         ]).
+
 %% Common code to run short sequences ==========================================
 
 expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->