From 44ceaf14093367e71071523fc65030202b0ef20e Mon Sep 17 00:00:00 2001 From: Mikael Pettersson Date: Mon, 27 Jul 2020 21:16:16 +0200 Subject: [PATCH] sim: sim_halfword: handle HRRE/HRREI/HRREM/HRRES, add unit tests --- erlang/apps/sim/src/sim_core.erl | 4 ++ erlang/apps/sim/src/sim_halfword.erl | 51 +++++++++++++++++ erlang/apps/sim/test/sim_halfword_tests.erl | 62 +++++++++++++++++++++ 3 files changed, 117 insertions(+) diff --git a/erlang/apps/sim/src/sim_core.erl b/erlang/apps/sim/src/sim_core.erl index 736e243..c8a0b9b 100644 --- a/erlang/apps/sim/src/sim_core.erl +++ b/erlang/apps/sim/src/sim_core.erl @@ -361,6 +361,10 @@ dispatch(Core, Mem, IR, EA) -> 8#561 -> sim_halfword:handle_HRROI(Core, Mem, IR, EA); 8#562 -> sim_halfword:handle_HRROM(Core, Mem, IR, EA); 8#563 -> sim_halfword:handle_HRROS(Core, Mem, IR, EA); + 8#570 -> sim_halfword:handle_HRRE(Core, Mem, IR, EA); + 8#571 -> sim_halfword:handle_HRREI(Core, Mem, IR, EA); + 8#572 -> sim_halfword:handle_HRREM(Core, Mem, IR, EA); + 8#573 -> sim_halfword:handle_HRRES(Core, Mem, IR, EA); _ -> PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset, {Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}} diff --git a/erlang/apps/sim/src/sim_halfword.erl b/erlang/apps/sim/src/sim_halfword.erl index 9d4f5c6..5d076f1 100644 --- a/erlang/apps/sim/src/sim_halfword.erl +++ b/erlang/apps/sim/src/sim_halfword.erl @@ -54,6 +54,10 @@ , handle_HRLZM/4 , handle_HRLZS/4 , handle_HRR/4 + , handle_HRRE/4 + , handle_HRREI/4 + , handle_HRREM/4 + , handle_HRRES/4 , handle_HRRI/4 , handle_HRRM/4 , handle_HRRO/4 @@ -547,6 +551,49 @@ handle_HRROS(Core, Mem, IR, EA) -> fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) end. +%% HRRE - Half Word Right to Right, Extend + +-spec handle_HRRE(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HRRE(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = set_right_extend(get_right(CE)), + sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + +-spec handle_HRREI(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HRREI(Core, Mem, IR, EA) -> + AC = IR band 8#17, + Word = set_right_extend(EA#ea.offset), + sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem). + +-spec handle_HRREM(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HRREM(Core, Mem, IR, EA) -> + AC = IR band 8#17, + CA = sim_core:get_ac(Core, AC), + Word = set_right_extend(get_right(CA)), + handle_writeback(Core, Mem, EA, Word). + +-spec handle_HRRES(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HRRES(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = set_right_extend(get_right(CE)), + handle_writeback(Core, Mem, AC, EA, Word); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + %% Miscellaneous =============================================================== handle_writeback(Core, Mem, EA, Word) -> @@ -588,3 +635,7 @@ set_left_zeros(Left) -> Left bsl 18. set_right(Word, Right) -> (Word band (((1 bsl 18) - 1) bsl 18)) bor Right. set_right_ones(Right) -> (((1 bsl 18) - 1) bsl 18) bor Right. + +set_right_extend(Right) -> + UInt18Sbit = 1 bsl (18 - 1), + ((Right bxor UInt18Sbit) - UInt18Sbit) band ((1 bsl 36) - 1). diff --git a/erlang/apps/sim/test/sim_halfword_tests.erl b/erlang/apps/sim/test/sim_halfword_tests.erl index 9888d41..49b7437 100644 --- a/erlang/apps/sim/test/sim_halfword_tests.erl +++ b/erlang/apps/sim/test/sim_halfword_tests.erl @@ -89,6 +89,10 @@ -define(OP_HRROI, 8#561). -define(OP_HRROM, 8#562). -define(OP_HRROS, 8#563). +-define(OP_HRRE, 8#570). +-define(OP_HRREI, 8#571). +-define(OP_HRREM, 8#572). +-define(OP_HRRES, 8#573). %% 2.8 Half-Word Data Transmission ============================================= @@ -751,6 +755,64 @@ hrros_no_ac_test() -> , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(0, 1)} % AC0 = 0,,1 ]). +%% HRRE - Half Word Right to Right, Extend + +hrre_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HRRE, 1, 0, 0, 8#200)} % 1,,101/ HRRE 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(0, -1)} % 1,,200/ 0,,-1 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, -1)} % AC1 = -1,,-1 + ]). + +hrrei_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HRREI, 1, 0, 0, 1)} % 1,,101/ HRREI 1,1 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1 + ]). + +hrrem_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HRREM, 1, 0, 0, 8#200)} % 1,,101/ HRREM 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1 + ]). + +hrres_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HRRES, 1, 0, 0, 8#200)} % 1,,101/ HRRES 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(0, -1)} % 1,,200/ 0,,-1 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(-1, -1)} % C(1,,200) = -1,,-1 + , {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, -1)} % AC1 = -1,,-1 + ]). + +hrres_no_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 0, 0, 0, 1)} % 1,,100/ MOVEI 0,1 + , {1, 8#101, ?INSN(?OP_HRRES, 0, 0, 0, 8#200)} % 1,,101/ HRRES 0,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(0, -1)} % 1,,200/ 0,,-1 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(-1, -1)} % C(1,,200) = -1,,-1 + , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(0, 1)} % AC0 = 0,,1 + ]). + %% Common code to run short sequences ========================================== expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->