diff --git a/erlang/apps/sim/src/sim_core.erl b/erlang/apps/sim/src/sim_core.erl
index 475808a..5d37d22 100644
--- a/erlang/apps/sim/src/sim_core.erl
+++ b/erlang/apps/sim/src/sim_core.erl
@@ -349,6 +349,10 @@ dispatch(Core, Mem, IR, EA) ->
     8#535 -> sim_halfword:handle_HRLEI(Core, Mem, IR, EA);
     8#536 -> sim_halfword:handle_HRLEM(Core, Mem, IR, EA);
     8#537 -> sim_halfword:handle_HRLES(Core, Mem, IR, EA);
+    8#540 -> sim_halfword:handle_HRR(Core, Mem, IR, EA);
+    8#541 -> sim_halfword:handle_HRRI(Core, Mem, IR, EA);
+    8#542 -> sim_halfword:handle_HRRM(Core, Mem, IR, EA);
+    8#543 -> sim_halfword:handle_HRRS(Core, Mem, IR, EA);
     _ ->
       PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
       {Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}
diff --git a/erlang/apps/sim/src/sim_halfword.erl b/erlang/apps/sim/src/sim_halfword.erl
index ef29823..edd498a 100644
--- a/erlang/apps/sim/src/sim_halfword.erl
+++ b/erlang/apps/sim/src/sim_halfword.erl
@@ -53,6 +53,10 @@
         , handle_HRLZ/4
         , handle_HRLZM/4
         , handle_HRLZS/4
+        , handle_HRR/4
+        , handle_HRRI/4
+        , handle_HRRM/4
+        , handle_HRRS/4
         ]).
 
 -include("sim_core.hrl").
@@ -408,6 +412,55 @@ handle_HRLES(Core, Mem, IR, EA) ->
                           fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
   end.
 
+%% HRR - Half Word Right to Right
+
+-spec handle_HRR(#core{}, sim_mem:mem(), IR :: word(), #ea{})
+      -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
+handle_HRR(Core, Mem, IR, EA) ->
+  case sim_core:c(Core, Mem, EA) of
+    {ok, CE} ->
+      AC = IR band 8#17,
+      CA = sim_core:get_ac(Core, AC),
+      Word = set_right(CA, get_right(CE)),
+      sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
+    {error, Reason} ->
+      sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
+                          fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
+  end.
+
+-spec handle_HRRI(#core{}, sim_mem:mem(), IR :: word(), #ea{})
+      -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
+handle_HRRI(Core, Mem, IR, EA) ->
+  AC = IR band 8#17,
+  CA = sim_core:get_ac(Core, AC),
+  Word = set_right(CA, EA#ea.offset),
+  sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem).
+
+-spec handle_HRRM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
+      -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
+handle_HRRM(Core, Mem, IR, EA) ->
+  case sim_core:c(Core, Mem, EA) of
+    {ok, CE} ->
+      AC = IR band 8#17,
+      CA = sim_core:get_ac(Core, AC),
+      Word = set_right(CE, get_right(CA)),
+      handle_writeback(Core, Mem, EA, Word);
+    {error, Reason} ->
+      sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
+                          fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
+  end.
+
+-spec handle_HRRS(#core{}, sim_mem:mem(), IR :: word(), #ea{})
+      -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
+handle_HRRS(Core, Mem, IR, EA) ->
+  %% The manual states: "If A is zero, HRRS is a no-op (that writes in memory);
+  %% otherwise, it is equivalent to MOVE."  This is a contradictory statement:
+  %% a MOVE A,E reads E but does not write to it.  Compare with HLLI, which has
+  %% a similar statement without the "(that writes in memory)" part.  For
+  %% consistency, treat HRRS like HLLS.  Alternatively both should perform the
+  %% redundant reads and writes, but then they are not equivalent to MOVE.
+  handle_HLLS(Core, Mem, IR, EA).
+
 %% Miscellaneous ===============================================================
 
 handle_writeback(Core, Mem, EA, Word) ->
@@ -445,3 +498,5 @@ set_left_extend(Left) ->
 set_left_ones(Left) -> (Left bsl 18) bor ((1 bsl 18) - 1).
 
 set_left_zeros(Left) -> Left bsl 18.
+
+set_right(Word, Right) -> (Word band (((1 bsl 18) - 1) bsl 18)) bor Right.
diff --git a/erlang/apps/sim/test/sim_halfword_tests.erl b/erlang/apps/sim/test/sim_halfword_tests.erl
index bca42ce..8c97425 100644
--- a/erlang/apps/sim/test/sim_halfword_tests.erl
+++ b/erlang/apps/sim/test/sim_halfword_tests.erl
@@ -77,6 +77,10 @@
 -define(OP_HRLEI, 8#535).
 -define(OP_HRLEM, 8#536).
 -define(OP_HRLES, 8#537).
+-define(OP_HRR,   8#540).
+-define(OP_HRRI,  8#541).
+-define(OP_HRRM,  8#542).
+-define(OP_HRRS,  8#543).
 
 %% 2.8 Half-Word Data Transmission =============================================
 
@@ -567,6 +571,62 @@ hrles_no_ac_test() ->
          , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(0, 1)} % AC0 = 0,,1
          ]).
 
+%% HRR - Half Word Right to Right
+
+hrr_test() ->
+  Prog =
+    [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)}     % 1,,100/ MOVSI 1,1
+    , {1, 8#101, ?INSN(?OP_HRR, 1, 0, 0, 8#200)}   % 1,,101/ HRR 1,200
+    , {1, 8#102, ?INSN_INVALID}                    % 1,,102/ <invalid>
+    , {1, 8#200, ?COMMA2(0, 1)}                    % 1,,200/ 0,,1
+    ],
+  expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
+         [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(1, 1)} % AC1 = 1,,1
+         ]).
+
+hrri_test() ->
+  Prog =
+    [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)}     % 0,,100/ MOVSI 1,1
+    , {1, 8#101, ?INSN(?OP_HRRI, 1, 0, 0, 1)}      % 0,,101/ HRRI 1,1
+    , {1, 8#102, ?INSN_INVALID}                    % 0,,102/ <invalid>
+    ],
+  expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
+         [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(1, 1)} % AC1 = 1,,1
+         ]).
+
+hrrm_test() ->
+  Prog =
+    [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)}     % 1,,100/ MOVEI 1,1
+    , {1, 8#101, ?INSN(?OP_HRRM, 1, 0, 0, 8#200)}  % 1,,101/ HRRM 1,200
+    , {1, 8#102, ?INSN_INVALID}                    % 1,,102/ <invalid>
+    , {1, 8#200, ?COMMA2(1, 0)}                    % 1,,200/ 1,,0
+    ],
+  expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
+         [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(1, 1)} % C(1,200) = 1,,1
+         ]).
+
+hrrs_ac_test() ->
+  Prog =
+    [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)}     % 1,,100/ MOVSI 1,1
+    , {1, 8#101, ?INSN(?OP_HRRS, 1, 0, 0, 8#200)}  % 1,,101/ HRRS 1,200
+    , {1, 8#102, ?INSN_INVALID}                    % 1,,102/ <invalid>
+    , {1, 8#200, ?COMMA2(0, 1)}                    % 1,,200/ 0,,1
+    ],
+  expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
+         [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1
+         ]).
+
+hrrs_no_ac_test() ->
+  Prog =
+    [ {1, 8#100, ?INSN(?OP_MOVSI, 0, 0, 0, 1)}     % 1,,100/ MOVSI 0,1
+    , {1, 8#101, ?INSN(?OP_HRRS, 0, 0, 0, 8#200)}  % 1,,101/ HRRS 0,200
+    , {1, 8#102, ?INSN_INVALID}                    % 1,,102/ <invalid>
+    , {1, 8#200, ?COMMA2(0, 1)}                    % 1,,200/ 0,,1
+    ],
+  expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
+         [ {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,0
+         ]).
+
 %% Common code to run short sequences ==========================================
 
 expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->