diff --git a/erlang/apps/sim/src/sim_core.erl b/erlang/apps/sim/src/sim_core.erl index 946a4de..736e243 100644 --- a/erlang/apps/sim/src/sim_core.erl +++ b/erlang/apps/sim/src/sim_core.erl @@ -357,6 +357,10 @@ dispatch(Core, Mem, IR, EA) -> 8#551 -> sim_moves:handle_MOVEI(Core, Mem, IR, EA); % HRRZI = MOVEI 8#552 -> sim_halfword:handle_HRRZM(Core, Mem, IR, EA); 8#553 -> sim_halfword:handle_HRRZS(Core, Mem, IR, EA); + 8#560 -> sim_halfword:handle_HRRO(Core, Mem, IR, EA); + 8#561 -> sim_halfword:handle_HRROI(Core, Mem, IR, EA); + 8#562 -> sim_halfword:handle_HRROM(Core, Mem, IR, EA); + 8#563 -> sim_halfword:handle_HRROS(Core, Mem, IR, EA); _ -> PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset, {Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}} diff --git a/erlang/apps/sim/src/sim_halfword.erl b/erlang/apps/sim/src/sim_halfword.erl index 0ddf8b4..9d4f5c6 100644 --- a/erlang/apps/sim/src/sim_halfword.erl +++ b/erlang/apps/sim/src/sim_halfword.erl @@ -56,6 +56,10 @@ , handle_HRR/4 , handle_HRRI/4 , handle_HRRM/4 + , handle_HRRO/4 + , handle_HRROI/4 + , handle_HRROM/4 + , handle_HRROS/4 , handle_HRRS/4 , handle_HRRZ/4 , handle_HRRZM/4 @@ -500,6 +504,49 @@ handle_HRRZS(Core, Mem, IR, EA) -> fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) end. +%% HRRO - Half Word Right to Right, Ones + +-spec handle_HRRO(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HRRO(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = set_right_ones(get_right(CE)), + sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + +-spec handle_HRROI(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HRROI(Core, Mem, IR, EA) -> + AC = IR band 8#17, + Word = set_right_ones(EA#ea.offset), + sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem). + +-spec handle_HRROM(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HRROM(Core, Mem, IR, EA) -> + AC = IR band 8#17, + CA = sim_core:get_ac(Core, AC), + Word = set_right_ones(get_right(CA)), + handle_writeback(Core, Mem, EA, Word). + +-spec handle_HRROS(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HRROS(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = set_right_ones(get_right(CE)), + handle_writeback(Core, Mem, AC, EA, Word); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + %% Miscellaneous =============================================================== handle_writeback(Core, Mem, EA, Word) -> @@ -539,3 +586,5 @@ set_left_ones(Left) -> (Left bsl 18) bor ((1 bsl 18) - 1). set_left_zeros(Left) -> Left bsl 18. set_right(Word, Right) -> (Word band (((1 bsl 18) - 1) bsl 18)) bor Right. + +set_right_ones(Right) -> (((1 bsl 18) - 1) bsl 18) bor Right. diff --git a/erlang/apps/sim/test/sim_halfword_tests.erl b/erlang/apps/sim/test/sim_halfword_tests.erl index 6b6c57d..9888d41 100644 --- a/erlang/apps/sim/test/sim_halfword_tests.erl +++ b/erlang/apps/sim/test/sim_halfword_tests.erl @@ -85,6 +85,10 @@ -define(OP_HRRZI, 8#551). -define(OP_HRRZM, 8#552). -define(OP_HRRZS, 8#553). +-define(OP_HRRO, 8#560). +-define(OP_HRROI, 8#561). +-define(OP_HRROM, 8#562). +-define(OP_HRROS, 8#563). %% 2.8 Half-Word Data Transmission ============================================= @@ -689,6 +693,64 @@ hrrzs_no_ac_test() -> , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,0 ]). +%% HRRO - Half Word Right to Right, Ones + +hrro_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HRRO, 1, 0, 0, 8#200)} % 1,,101/ HRRO 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(0, 2)} % 1,,200/ 0,,2 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, 2)} % AC1 = -1,,2 + ]). + +hrroi_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HRROI, 1, 0, 0, 2)} % 1,,101/ HRROI 1,2 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, 2)} % AC1 = -1,,2 + ]). + +hrrom_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 2)} % 1,,100/ MOVEI 1,2 + , {1, 8#101, ?INSN(?OP_HRROM, 1, 0, 0, 8#200)} % 1,,101/ HRROM 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(0, 1)} % 1,,200/ 0,,1 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(-1, 2)} % C(1,,200) = -1,,2 + ]). + +hrros_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HRROS, 1, 0, 0, 8#200)} % 1,,101/ HRROS 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(0, 2)} % 1,,200/ 0,,2 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(-1, 2)} % C(1,,200) = -1,,2 + , {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, 2)} % AC1 = -1,,2 + ]). + +hrros_no_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 0, 0, 0, 1)} % 1,,100/ MOVEI 0,1 + , {1, 8#101, ?INSN(?OP_HRROS, 1, 0, 0, 8#200)} % 1,,101/ HRROS 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(0, 2)} % 1,,200/ 0,,2 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(-1, 2)} % C(1,,200) = -1,,2 + , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(0, 1)} % AC0 = 0,,1 + ]). + %% Common code to run short sequences ========================================== expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->