diff --git a/erlang/apps/sim/src/sim_core.erl b/erlang/apps/sim/src/sim_core.erl index 868fb83..e1aa2ac 100644 --- a/erlang/apps/sim/src/sim_core.erl +++ b/erlang/apps/sim/src/sim_core.erl @@ -377,6 +377,10 @@ dispatch(Core, Mem, IR, EA) -> 8#571 -> sim_halfword:handle_HRREI(Core, Mem, IR, EA); 8#572 -> sim_halfword:handle_HRREM(Core, Mem, IR, EA); 8#573 -> sim_halfword:handle_HRRES(Core, Mem, IR, EA); + 8#574 -> sim_halfword:handle_HLRE(Core, Mem, IR, EA); + 8#575 -> sim_boolean:handle_SETZ(Core, Mem, IR, EA); % HLREI = HLRZI = SETZ + 8#576 -> sim_halfword:handle_HLREM(Core, Mem, IR, EA); + 8#577 -> sim_halfword:handle_HLRES(Core, Mem, IR, EA); _ -> PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset, {Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}} diff --git a/erlang/apps/sim/src/sim_halfword.erl b/erlang/apps/sim/src/sim_halfword.erl index 71c0147..3adce1f 100644 --- a/erlang/apps/sim/src/sim_halfword.erl +++ b/erlang/apps/sim/src/sim_halfword.erl @@ -39,6 +39,9 @@ , handle_HLLZM/4 , handle_HLLZS/4 , handle_HLR/4 + , handle_HLRE/4 + , handle_HLREM/4 + , handle_HLRES/4 , handle_HLRI/4 , handle_HLRM/4 , handle_HLRO/4 @@ -735,6 +738,42 @@ handle_HLROS(Core, Mem, IR, EA) -> fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) end. +%% HLRE - Half Word Left to Right, Extend + +-spec handle_HLRE(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLRE(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = set_right_extend(get_left(CE)), + sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + +-spec handle_HLREM(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLREM(Core, Mem, IR, EA) -> + AC = IR band 8#17, + CA = sim_core:get_ac(Core, AC), + Word = set_right_extend(get_left(CA)), + handle_writeback(Core, Mem, EA, Word). + +-spec handle_HLRES(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLRES(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = set_right_extend(get_left(CE)), + handle_writeback(Core, Mem, AC, EA, Word); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + %% Miscellaneous =============================================================== handle_writeback(Core, Mem, EA, Word) -> diff --git a/erlang/apps/sim/test/sim_halfword_tests.erl b/erlang/apps/sim/test/sim_halfword_tests.erl index 91d230b..045c561 100644 --- a/erlang/apps/sim/test/sim_halfword_tests.erl +++ b/erlang/apps/sim/test/sim_halfword_tests.erl @@ -105,6 +105,10 @@ -define(OP_HRREI, 8#571). -define(OP_HRREM, 8#572). -define(OP_HRRES, 8#573). +-define(OP_HLRE, 8#574). +-define(OP_HLREI, 8#575). +-define(OP_HLREM, 8#576). +-define(OP_HLRES, 8#577). %% 2.8 Half-Word Data Transmission ============================================= @@ -999,6 +1003,64 @@ hlros_no_ac_test() -> , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,1 ]). +%% HLRE - Half Word Left to Right, Extend + +hlre_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HLRE, 1, 0, 0, 8#200)} % 1,,101/ HLRE 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(8#400000, 0)} % 1,,200/ 400000,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, 8#400000)} % AC1 = -1,,400000 + ]). + +hlrei_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HLREI, 1, 0, 0, 1)} % 1,,101/ HLREI 1,1 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 0)} % AC1 = 0,,0 + ]). + +hlrem_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HLREM, 1, 0, 0, 8#200)} % 1,,101/ HLREM 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1 + ]). + +hlres_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HLRES, 1, 0, 0, 8#200)} % 1,,101/ HLRES 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(8#400000, 0)} % 1,,200/ 400000,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(-1, 8#400000)} % C(1,,200) = -1,,400000 + , {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, 8#400000)} % AC1 = -1,,400000 + ]). + +hlres_no_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 0, 0, 0, 1)} % 1,,100/ MOVSI 0,1 + , {1, 8#101, ?INSN(?OP_HLRES, 0, 0, 0, 8#200)} % 1,,101/ HLRES 0,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1 + , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,0 + ]). + %% Common code to run short sequences ========================================== expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->