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pdp10-opcodes: complete rewrite
This commit is contained in:
Mikael Pettersson
@@ -1,43 +1,52 @@
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/* PDP-10 opcode list.
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Copyright (C) 2000 Free Software Foundation, Inc.
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This file is part of GDB and GAS.
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GDB and GAS are free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 1, or (at your option)
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any later version.
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GDB and GAS are distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GDB or GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef PDP10_OPCODES_H
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#define PDP10_OPCODES_H
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/*
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* PDP-10 notational conventions.
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* pdp10-opcodes.h
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* Copyright (C) 2013-2015 Mikael Pettersson
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*
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* A word is 36 bits wide, with bits numbered 0 to 35, left to right
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* (most significant to least significant).
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* This file is part of pdp10-tools.
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*
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* A doubleword is two adjacent words treated as a single 72-bit entity,
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* where the word with the lower address is on the left. The direction
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* from more to less significance is always from lower to higher addresses.
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* pdp10-tools is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* Bit numbers are always displayed in decimal. Values in bit fields,
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* especially opcodes, are always displayed in octal.
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* pdp10-tools is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with pdp10-tools. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* PDP-10 instruction types.
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* Word Representation
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* ===================
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*
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* Most PDP-10 instructions have this format:
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*
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* 11111111112222222222333333
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* 012345678901234567890123456789012345
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* +------------------------------------+
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* | |
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* +------------------------------------+
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*
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* The basic storage unit is a 36-bit wide word. Its bits are numbered 0
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* to 35, in left-to-right order, with bit 0 being the most significant
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* and bit 35 the least significant. (Similar to IBM's bit numbering but
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* opposite to most modern processors.)
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*
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* The architecture supports sub-word storage units via special instructions
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* and specially formatted "byte" pointers, where a byte may be from 0 to 36
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* bits wide. Incrementing a byte pointer moves it right over a word towards
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* its less significant bits, implying a big-endian storage model.
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*
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* A 72-bit long integer is composed of two adjacent words. It stores the most
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* significant bits in first word (lower address) and the least significant bits
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* in the second word (higher address), again implying a big-endian storage model.
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*
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*
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* Instruction Representation
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* ==========================
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*
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* Basic instructions are stored in 36-bit words with the following format:
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*
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* 111 1 1111 112222222222333333
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* 012345678 9012 3 4567 890123456789012345
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@@ -46,21 +55,22 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307
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* +---------+----+-+----+------------------+
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* 9 bits 4 1 4 18 bits
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*
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* A usually specifies the accumulator.
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* I indicates indirect addressing.
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* X specifies the index register.
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* Y specifies the address.
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* A 9-bit opcode is stored in the high 9 bits.
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* A is a 4-bit field specifying the accumulator (a register).
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* I is a 1-bit field specifying indirect addressing.
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* X is a 4-bit field specifying the index register.
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* Y is an 18-bit field specifying an address or offset.
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*
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* I, X, and Y are used together to calculate E, the effective address.
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* E, the effective addreess, is computed from I, X, and Y.
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*
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* PDP10_A_OPCODE means that A is used together with the opcode field
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* to specify the operation.
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* In some instructions A contains further opcode bits.
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*
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* PDP10_A_UNUSED means that A is unused and should be set to zero.
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* In some instructions A is unused and should be zero.
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*
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* PDP10_E_UNUSED means that I, X, and Y are unused and should be set to zero.
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* Instructions that not compute an effective address E
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* should have I, X, and Y set to zero.
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*
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* PDP10_IO means that the instruction format looks like this:
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* IO instructions have a slightly different format:
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*
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* 111 1 1111 112222222222333333
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* 012 3456789 012 3 4567 890123456789012345
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@@ -69,69 +79,163 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307
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* +---+-------+---+-+----+------------------+
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* 3 7 bits 3 1 4 18 bits
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*
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* op1 and op2 are used together to specify the operation.
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* The op1 field is all-bits-one (7), the device field addresses the selected device,
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* and the op2 field specifies the operation. Both devices internal to the processor
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* and devices attached via external buses can be accessed.
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*
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* I, X, and Y as above.
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* Some non-IO instructions also have a 7 in their high three bits.
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*
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* PDP10_EXTEND means that this the first word of a two-word
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* instruction. The second word is located at the effective address,
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* E, of the first instruction word.
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* Extended instructions consist of two separate instruction words:
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*
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* A:
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* 111 1 1111 112222222222333333
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* 012345678 9012 3 4567 890123456789012345
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* +---------+----+-+----+------------------+
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* | 0123 | A |I| X | Y |
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* +---------+----+-+----+------------------+
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* 9 bits 4 1 4 18 bits
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*
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* E0:
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* 111 1 1111 112222222222333333
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* 012345678 9012 3 4567 890123456789012345
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* +---------+----+-+----+------------------+
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* | xopcode |0000|I| X | Y |
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* +---------+----+-+----+------------------+
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* 9 bits 4 1 4 18 bits
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*
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* The first word is stored at address A in the instruction stream in the basic
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* format with opcode 0123. The second word is stored at the effective address
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* E0 specified by the the first word. Its accumulator field is unused and must
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* be zero for compatibility with future extensions.
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*/
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#define PDP10_BASIC 0x00
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#define PDP10_A_OPCODE 0x01
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#define PDP10_A_UNUSED 0x02
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#define PDP10_E_UNUSED 0x04
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#define PDP10_IO 0x08
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#define PDP10_EXTEND 0x10
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/*
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* PDP-10 CPU models.
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* Known PDP10 CPU models, each represented by a distinct bit value.
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*
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* These are combined with bit-wise 'and', 'or', and 'not' operations
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* to form sets of CPU models, used to check if a given mnemonic or
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* opcode is available for a selected set of CPUs.
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*/
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#define PDP10_NONE 0x00000000
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#define PDP6_166 0x00000001 /* DEC PDP-6 Type 166 Arithmetic Processor */
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#define PDP10_KA10 0x00000002 /* DEC PDP-10 KA10 */
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#define PDP10_KA10_ITS 0x00000004 /* DEC PDP-10 KA10, modifications for ITS */
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#define PDP10_KI10 0x00000008 /* DEC PDP-10 KI10 */
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#define PDP10_KL10 0x00000010 /* DEC PDP-10 KL10 */
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#define PDP10_KL10_ITS 0x00000020 /* DEC PDP-10 KL10, ITS microcode */
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#define PDP10_KL10_271 0x00000040 /* DEC PDP-10 KL10, microcode version >= 271 */
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#define PDP10_KS10 0x00000080 /* DEC PDP-10 KS10 */
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#define PDP10_KS10_ITS 0x00000100 /* DEC PDP-10 KS10, ITS microcode */
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#define PDP10_KC10 0x00000200 /* DEC PDP-10 KC10 */
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#define PDP10_XKL1 0x00000400 /* XKL TOAD-1 XKL-1 */
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#define PDP10_ALL 0xffffffff
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enum {
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/*
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* DEC processors.
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*/
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struct pdp10_instruction
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{
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const char *name;
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unsigned int opcode;
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unsigned int type;
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unsigned int model;
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PDP10_NONE = 0,
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PDP6_166 = 1 << 0, /* DEC PDP-6 Type 166 Arithmetic Processor */
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PDP10_KA10 = 1 << 1, /* DEC PDP-10 KA10 */
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PDP10_KA10_ITS = 1 << 2, /* DEC PDP-10 KA10, ITS microcode */
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PDP10_KI10 = 1 << 3, /* DEC PDP-10 KI10 */
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PDP10_KL10 = 1 << 4, /* DEC PDP-10 KL10 */
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PDP10_KL10_ITS = 1 << 5, /* DEC PDP-10 KL10, ITS microcode */
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PDP10_KL10_271 = 1 << 6, /* DEC PDP-10 KL10, microcode version >= 271 (many extensions) */
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PDP10_KS10 = 1 << 7, /* DEC PDP-10 KS10 */
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PDP10_KS10_ITS = 1 << 8, /* DEC PDP-10 KS10, ITS microcode */
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PDP10_KC10 = 1 << 9, /* DEC PDP-10 KC10 (Jupiter, full extended addressing) */
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PDP10_KD10 = 1 << 10, /* DEC PDP-10 KD10 (Minnow, KS10 extended to match KC10 specs) */
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/*
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* XKL Processors.
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*
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* The XKL-2 is believed to have been built, and to contain some instruction set
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* extensions, but no details are known about it at this time.
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*/
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PDP10_XKL1 = 1 << 11, /* XKL TOAD-1 XKL-1, KL10 clone with KC10-like full extended addressing */
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/*
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* Other clones, not yet supported.
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*
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* System Concepts SC-20, SC-25, SC-30M, SC-40 (KC10-like)
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*
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* Foonly F-1, F-2, F-3, F-4 (KI10/KL10-hybrid)
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*
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* Xerox PARC MAXC (KI10-like?)
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*/
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/*
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* Convenience constants for combinations of CPU models.
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*/
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PDP10_ALL = PDP10_XKL1 | (PDP10_XKL1 - 1), /* XXX: depends on XKL1 being last above */
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PDP10_KL10_271up = PDP10_KL10_271 | PDP10_XKL1,
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PDP10_KL10any = PDP10_KL10 | PDP10_KL10_ITS | PDP10_KL10_271up,
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PDP10_KL10up = PDP10_KL10any | PDP10_KS10,
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PDP10_KI10_to_KL10 = PDP10_KI10 | PDP10_KL10any,
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PDP10_KI10up = PDP10_KI10 | PDP10_KL10up,
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PDP10_KA10any = PDP10_KA10 | PDP10_KA10_ITS,
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PDP10_KA10up = PDP10_KA10any | PDP10_KI10up,
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PDP10_KA10_to_KI10 = PDP10_KA10 | PDP10_KI10, /* XXX: should that be KA10_any? */
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PDP10_KA10_to_KL10 = PDP10_KA10_to_KI10 | PDP10_KL10any,
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PDP10_not_KS10_or_XKL1 = PDP10_ALL & ~(PDP10_KS10 | PDP10_XKL1), /* XXX: should that be KS10_any? */
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PDP10_ITS = PDP10_KA10_ITS | PDP10_KL10_ITS | PDP10_KS10_ITS,
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PDP6_166_to_PDP10_KI10 = PDP6_166 | PDP10_KA10_to_KI10,
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};
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struct pdp10_device
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{
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const char *name;
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unsigned number;
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unsigned int model;
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typedef unsigned short pdp10_cpu_models_t;
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/*
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* Device names for IO instructions.
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*/
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struct pdp10_cpu_device {
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const char *name;
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unsigned char device; /* device field in bits 3-9 of IO instructions */
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pdp10_cpu_models_t models;
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};
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extern const struct pdp10_instruction pdp10_instruction[];
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extern const unsigned int pdp10_num_instructions;
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const struct pdp10_cpu_device *
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pdp10_cpu_device_from_name(pdp10_cpu_models_t models, const char *name);
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extern const struct pdp10_device pdp10_device[];
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extern const unsigned int pdp10_num_devices;
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/*
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* Instructions.
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*/
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extern const struct pdp10_instruction pdp10_alias[];
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extern const unsigned int pdp10_num_aliases;
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enum {
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/* Each instruction belongs to exactly one of these primary categories,
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which determine how the high 13 bits are to be interpreted: */
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/* XXX: change this to separate mutually exclusive bits to simplify usage */
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PDP10_INSN_BASIC = 0,
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PDP10_INSN_A_OPCODE = 1,
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PDP10_INSN_A_UNUSED = 2,
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PDP10_INSN_IO = 3,
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extern const struct pdp10_instruction pdp10_extended_instruction[];
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extern const unsigned int pdp10_num_extended_instructions;
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/* Flag set to indicate that E is unused. */
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PDP10_INSN_E_UNUSED = 4,
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const struct pdp10_instruction *pdp10_instruction_from_high13(unsigned int high13);
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/* Flag set to indicate that this is the second word of an extended instruction. */
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PDP10_INSN_EXTENDED = 8,
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};
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const struct pdp10_instruction *pdp10_instruction_from_name(const char *name);
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typedef unsigned char pdp10_insn_fmt_t;
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#endif /* PDP10_OPCODES_H */
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struct pdp10_insn {
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const char *name;
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/*
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* The high13 field is 13 bits, formatted as:
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* <9 bit opcode><0000> BASIC, A_UNUSED
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* <9 + 4 bit opcode> A_OPCODE
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* <111><0000000><3 bit op> IO
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*
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* An extended instruction uses the BASIC format with opcode 0123 for
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* the first word, and the A_UNUSED | EXTENDED format for the second word.
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*/
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unsigned short high13;
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pdp10_insn_fmt_t fmt;
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pdp10_cpu_models_t models;
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};
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/* for assembly */
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const struct pdp10_insn *
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pdp10_insn_from_name(pdp10_cpu_models_t models, const char *name);
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/* for disassembly */
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const struct pdp10_insn *
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pdp10_insn_from_high13(pdp10_cpu_models_t models, unsigned int high13, int extended);
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