From ba24bbbbf1023b9022ec36da034cc044d9b25fda Mon Sep 17 00:00:00 2001 From: Mikael Pettersson Date: Mon, 27 Jul 2020 19:43:37 +0200 Subject: [PATCH] sim: sim_halfword: handle HRRZ/HRRZM/HRRZS, sim_core: handle HRRZI as MOVEI, add unit tests --- erlang/apps/sim/src/sim_core.erl | 4 ++ erlang/apps/sim/src/sim_halfword.erl | 39 +++++++++++++ erlang/apps/sim/test/sim_halfword_tests.erl | 62 +++++++++++++++++++++ 3 files changed, 105 insertions(+) diff --git a/erlang/apps/sim/src/sim_core.erl b/erlang/apps/sim/src/sim_core.erl index 5d37d22..946a4de 100644 --- a/erlang/apps/sim/src/sim_core.erl +++ b/erlang/apps/sim/src/sim_core.erl @@ -353,6 +353,10 @@ dispatch(Core, Mem, IR, EA) -> 8#541 -> sim_halfword:handle_HRRI(Core, Mem, IR, EA); 8#542 -> sim_halfword:handle_HRRM(Core, Mem, IR, EA); 8#543 -> sim_halfword:handle_HRRS(Core, Mem, IR, EA); + 8#550 -> sim_halfword:handle_HRRZ(Core, Mem, IR, EA); + 8#551 -> sim_moves:handle_MOVEI(Core, Mem, IR, EA); % HRRZI = MOVEI + 8#552 -> sim_halfword:handle_HRRZM(Core, Mem, IR, EA); + 8#553 -> sim_halfword:handle_HRRZS(Core, Mem, IR, EA); _ -> PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset, {Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}} diff --git a/erlang/apps/sim/src/sim_halfword.erl b/erlang/apps/sim/src/sim_halfword.erl index edd498a..0ddf8b4 100644 --- a/erlang/apps/sim/src/sim_halfword.erl +++ b/erlang/apps/sim/src/sim_halfword.erl @@ -57,6 +57,9 @@ , handle_HRRI/4 , handle_HRRM/4 , handle_HRRS/4 + , handle_HRRZ/4 + , handle_HRRZM/4 + , handle_HRRZS/4 ]). -include("sim_core.hrl"). @@ -461,6 +464,42 @@ handle_HRRS(Core, Mem, IR, EA) -> %% redundant reads and writes, but then they are not equivalent to MOVE. handle_HLLS(Core, Mem, IR, EA). +%% HRRZ - Half Word Right to Right, Zeros + +-spec handle_HRRZ(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HRRZ(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = get_right(CE), + sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + +-spec handle_HRRZM(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HRRZM(Core, Mem, IR, EA) -> + AC = IR band 8#17, + CA = sim_core:get_ac(Core, AC), + Word = get_right(CA), + handle_writeback(Core, Mem, EA, Word). + +-spec handle_HRRZS(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HRRZS(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = get_right(CE), + handle_writeback(Core, Mem, AC, EA, Word); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + %% Miscellaneous =============================================================== handle_writeback(Core, Mem, EA, Word) -> diff --git a/erlang/apps/sim/test/sim_halfword_tests.erl b/erlang/apps/sim/test/sim_halfword_tests.erl index 8c97425..6b6c57d 100644 --- a/erlang/apps/sim/test/sim_halfword_tests.erl +++ b/erlang/apps/sim/test/sim_halfword_tests.erl @@ -81,6 +81,10 @@ -define(OP_HRRI, 8#541). -define(OP_HRRM, 8#542). -define(OP_HRRS, 8#543). +-define(OP_HRRZ, 8#550). +-define(OP_HRRZI, 8#551). +-define(OP_HRRZM, 8#552). +-define(OP_HRRZS, 8#553). %% 2.8 Half-Word Data Transmission ============================================= @@ -627,6 +631,64 @@ hrrs_no_ac_test() -> [ {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,0 ]). +%% HRRZ - Half Word Right to Right, Zeros + +hrrz_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HRRZ, 1, 0, 0, 8#200)} % 1,,101/ HRRZ 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(0, 1)} % 1,,200/ 0,,1 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1 + ]). + +hrrzi_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 0,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HRRZI, 1, 0, 0, 1)} % 0,,101/ HRRZI 1,1 + , {1, 8#102, ?INSN_INVALID} % 0,,102/ + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1 + ]). + +hrrzm_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HRRZM, 1, 0, 0, 8#200)} % 1,,101/ HRRZM 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,200) = 0,,1 + ]). + +hrrzs_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HRRZS, 1, 0, 0, 8#200)} % 1,,101/ HRRZS 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 1)} % 1,,200/ 1,,1 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1 + , {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1 + ]). + +hrrzs_no_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 0, 0, 0, 1)} % 1,,100/ MOVSI 0,1 + , {1, 8#101, ?INSN(?OP_HRRZS, 0, 0, 0, 8#200)} % 1,,101/ HRRZS 0,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 1)} % 1,,200/ 1,,1 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1 + , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,0 + ]). + %% Common code to run short sequences ========================================== expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->