diff --git a/erlang/apps/sim/src/sim_core.erl b/erlang/apps/sim/src/sim_core.erl index c6ea786..868fb83 100644 --- a/erlang/apps/sim/src/sim_core.erl +++ b/erlang/apps/sim/src/sim_core.erl @@ -369,6 +369,10 @@ dispatch(Core, Mem, IR, EA) -> 8#561 -> sim_halfword:handle_HRROI(Core, Mem, IR, EA); 8#562 -> sim_halfword:handle_HRROM(Core, Mem, IR, EA); 8#563 -> sim_halfword:handle_HRROS(Core, Mem, IR, EA); + 8#564 -> sim_halfword:handle_HLRO(Core, Mem, IR, EA); + 8#565 -> sim_halfword:handle_HLROI(Core, Mem, IR, EA); + 8#566 -> sim_halfword:handle_HLROM(Core, Mem, IR, EA); + 8#567 -> sim_halfword:handle_HLROS(Core, Mem, IR, EA); 8#570 -> sim_halfword:handle_HRRE(Core, Mem, IR, EA); 8#571 -> sim_halfword:handle_HRREI(Core, Mem, IR, EA); 8#572 -> sim_halfword:handle_HRREM(Core, Mem, IR, EA); diff --git a/erlang/apps/sim/src/sim_halfword.erl b/erlang/apps/sim/src/sim_halfword.erl index 8fcdfba..71c0147 100644 --- a/erlang/apps/sim/src/sim_halfword.erl +++ b/erlang/apps/sim/src/sim_halfword.erl @@ -41,6 +41,10 @@ , handle_HLR/4 , handle_HLRI/4 , handle_HLRM/4 + , handle_HLRO/4 + , handle_HLROI/4 + , handle_HLROM/4 + , handle_HLROS/4 , handle_HLRS/4 , handle_HLRZ/4 , handle_HLRZM/4 @@ -688,6 +692,49 @@ handle_HLRZS(Core, Mem, IR, EA) -> fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) end. +%% HLRO - Half Word Left to Right, Ones + +-spec handle_HLRO(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLRO(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = set_right_ones(get_left(CE)), + sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + +-spec handle_HLROI(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLROI(Core, Mem, IR, _EA) -> + AC = IR band 8#17, + Word = ((1 bsl 18) - 1) bsl 18, + sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem). + +-spec handle_HLROM(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLROM(Core, Mem, IR, EA) -> + AC = IR band 8#17, + CA = sim_core:get_ac(Core, AC), + Word = set_right_ones(get_left(CA)), + handle_writeback(Core, Mem, EA, Word). + +-spec handle_HLROS(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLROS(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = set_right_ones(get_left(CE)), + handle_writeback(Core, Mem, AC, EA, Word); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + %% Miscellaneous =============================================================== handle_writeback(Core, Mem, EA, Word) -> diff --git a/erlang/apps/sim/test/sim_halfword_tests.erl b/erlang/apps/sim/test/sim_halfword_tests.erl index b65eb7c..91d230b 100644 --- a/erlang/apps/sim/test/sim_halfword_tests.erl +++ b/erlang/apps/sim/test/sim_halfword_tests.erl @@ -97,6 +97,10 @@ -define(OP_HRROI, 8#561). -define(OP_HRROM, 8#562). -define(OP_HRROS, 8#563). +-define(OP_HLRO, 8#564). +-define(OP_HLROI, 8#565). +-define(OP_HLROM, 8#566). +-define(OP_HLROS, 8#567). -define(OP_HRRE, 8#570). -define(OP_HRREI, 8#571). -define(OP_HRREM, 8#572). @@ -937,6 +941,64 @@ hlrzs_no_ac_test() -> , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 0,,1 ]). +%% HLRO - Half Word Left to Right, Ones + +hlro_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HLRO, 1, 0, 0, 8#200)} % 1,,101/ HLRO 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, 1)} % AC1 = -1,,1 + ]). + +hlroi_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HLROI, 1, 0, 0, 2)} % 1,,101/ HLROI 1,2 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, 0)} % AC1 = -1,,0 + ]). + +hlrom_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HLROM, 1, 0, 0, 8#200)} % 1,,101/ HLROM 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(-1, 1)} % C(1,,200) = -1,,1 + ]). + +hlros_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HLROS, 1, 0, 0, 8#200)} % 1,,101/ HLROS 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(-1, 1)} % C(1,,200) = -1,,1 + , {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, 1)} % AC1 = -1,,1 + ]). + +hlros_no_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 0, 0, 0, 1)} % 1,,100/ MOVSI 0,1 + , {1, 8#101, ?INSN(?OP_HLROS, 0, 0, 0, 8#200)} % 1,,101/ HLROS 0,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(-1, 1)} % C(1,,200) = -1,,1 + , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,1 + ]). + %% Common code to run short sequences ========================================== expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->