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sim: sim_boolean: handle SETCAB, add unit test

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This commit is contained in:
Mikael Pettersson
2020-07-25 15:12:01 +02:00
parent 9f273f13ec
commit d2e87ee401
3 changed files with 23 additions and 0 deletions
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9
erlang/apps/sim/src/sim_boolean.erl
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@@ -49,6 +49,7 @@
, handle_IORI/4
, handle_IORM/4
, handle_SETCA/4
, handle_SETCAB/4
, handle_SETCAM/4
, handle_SETMB/4
, handle_SETMI/4
@@ -533,6 +534,14 @@ handle_SETCAM(Core, Mem, IR, EA) ->
Word = (bnot CA) band ((1 bsl 36) - 1),
handle_ANDM_1(Core, Mem, EA, Word).
-spec handle_SETCAB(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_SETCAB(Core, Mem, IR, EA) ->
AC = IR band 8#17,
CA = sim_core:get_ac(Core, AC),
Word = (bnot CA) band ((1 bsl 36) - 1),
handle_ANDB(Core, Mem, AC, EA, Word).
%% Miscellaneous ===============================================================
ea_address(#ea{section = Section, offset = Offset}) ->

1
erlang/apps/sim/src/sim_core.erl
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@@ -296,6 +296,7 @@ dispatch(Core, Mem, IR, EA) ->
8#450 -> sim_boolean:handle_SETCA(Core, Mem, IR, EA);
8#451 -> sim_boolean:handle_SETCA(Core, Mem, IR, EA); % SETCAI = SETCA
8#452 -> sim_boolean:handle_SETCAM(Core, Mem, IR, EA);
8#453 -> sim_boolean:handle_SETCAB(Core, Mem, IR, EA);
_ ->
PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
{Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}