From d97d9c8efe7d1369bb60c2d076fd76a70aaf2595 Mon Sep 17 00:00:00 2001 From: Mikael Pettersson Date: Mon, 27 Jul 2020 23:28:01 +0200 Subject: [PATCH] sim: sim_halfword: handle HLRZ/HLRZM/HLRZS, sim_core: handle HLRZI as SETZ, add unit tests --- erlang/apps/sim/src/sim_core.erl | 4 ++ erlang/apps/sim/src/sim_halfword.erl | 39 +++++++++++++ erlang/apps/sim/test/sim_halfword_tests.erl | 62 +++++++++++++++++++++ 3 files changed, 105 insertions(+) diff --git a/erlang/apps/sim/src/sim_core.erl b/erlang/apps/sim/src/sim_core.erl index 37c3b8d..c6ea786 100644 --- a/erlang/apps/sim/src/sim_core.erl +++ b/erlang/apps/sim/src/sim_core.erl @@ -361,6 +361,10 @@ dispatch(Core, Mem, IR, EA) -> 8#551 -> sim_moves:handle_MOVEI(Core, Mem, IR, EA); % HRRZI = MOVEI 8#552 -> sim_halfword:handle_HRRZM(Core, Mem, IR, EA); 8#553 -> sim_halfword:handle_HRRZS(Core, Mem, IR, EA); + 8#554 -> sim_halfword:handle_HLRZ(Core, Mem, IR, EA); + 8#555 -> sim_boolean:handle_SETZ(Core, Mem, IR, EA); % HLRZI = HLLZI = SETZ + 8#556 -> sim_halfword:handle_HLRZM(Core, Mem, IR, EA); + 8#557 -> sim_halfword:handle_HLRZS(Core, Mem, IR, EA); 8#560 -> sim_halfword:handle_HRRO(Core, Mem, IR, EA); 8#561 -> sim_halfword:handle_HRROI(Core, Mem, IR, EA); 8#562 -> sim_halfword:handle_HRROM(Core, Mem, IR, EA); diff --git a/erlang/apps/sim/src/sim_halfword.erl b/erlang/apps/sim/src/sim_halfword.erl index 2c5c0ad..8fcdfba 100644 --- a/erlang/apps/sim/src/sim_halfword.erl +++ b/erlang/apps/sim/src/sim_halfword.erl @@ -42,6 +42,9 @@ , handle_HLRI/4 , handle_HLRM/4 , handle_HLRS/4 + , handle_HLRZ/4 + , handle_HLRZM/4 + , handle_HLRZS/4 , handle_HRL/4 , handle_HRLE/4 , handle_HRLEI/4 @@ -649,6 +652,42 @@ handle_HLRS(Core, Mem, IR, EA) -> fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) end. +%% HLRZ - Half Word Left to Right, Zeros + +-spec handle_HLRZ(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLRZ(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = get_left(CE), + sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + +-spec handle_HLRZM(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLRZM(Core, Mem, IR, EA) -> + AC = IR band 8#17, + CA = sim_core:get_ac(Core, AC), + Word = get_left(CA), + handle_writeback(Core, Mem, EA, Word). + +-spec handle_HLRZS(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLRZS(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = get_left(CE), + handle_writeback(Core, Mem, AC, EA, Word); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + %% Miscellaneous =============================================================== handle_writeback(Core, Mem, EA, Word) -> diff --git a/erlang/apps/sim/test/sim_halfword_tests.erl b/erlang/apps/sim/test/sim_halfword_tests.erl index 9e7439c..b65eb7c 100644 --- a/erlang/apps/sim/test/sim_halfword_tests.erl +++ b/erlang/apps/sim/test/sim_halfword_tests.erl @@ -89,6 +89,10 @@ -define(OP_HRRZI, 8#551). -define(OP_HRRZM, 8#552). -define(OP_HRRZS, 8#553). +-define(OP_HLRZ, 8#554). +-define(OP_HLRZI, 8#555). +-define(OP_HLRZM, 8#556). +-define(OP_HLRZS, 8#557). -define(OP_HRRO, 8#560). -define(OP_HRROI, 8#561). -define(OP_HRROM, 8#562). @@ -875,6 +879,64 @@ hlrs_no_ac_test() -> , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,0 ]). +%% HLRZ - Half Word Left to Right, Zeros + +hlrz_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HLRZ, 1, 0, 0, 8#200)} % 1,,101/ HLRZ 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1 + ]). + +hlrzi_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 0,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HLRZI, 1, 0, 0, 1)} % 0,,101/ HLRZI 1,1 + , {1, 8#102, ?INSN_INVALID} % 0,,102/ + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 0)} % AC1 = 0,,0 + ]). + +hlrzm_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HLRZM, 1, 0, 0, 8#200)} % 1,,101/ HLRZM 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,200) = 0,,1 + ]). + +hlrzs_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HLRZS, 1, 0, 0, 8#200)} % 1,,101/ HLRZS 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1 + , {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 1)} % AC1 = 0,,1 + ]). + +hlrzs_no_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 0, 0, 0, 1)} % 1,,100/ MOVSI 0,1 + , {1, 8#101, ?INSN(?OP_HLRZS, 0, 0, 0, 8#200)} % 1,,101/ HLRZS 0,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1 + , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 0,,1 + ]). + %% Common code to run short sequences ========================================== expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->