From df8b526bbd003a1bea93d85e6d6a558b5582962d Mon Sep 17 00:00:00 2001
From: Mikael Pettersson <mikpelinux@gmail.com>
Date: Wed, 22 Jul 2020 23:31:46 +0200
Subject: [PATCH] sim: sim_boolean: handle ANDM, add unit test

---
 erlang/apps/sim/src/sim_boolean.erl        | 23 ++++++++++++++++++++++
 erlang/apps/sim/src/sim_core.erl           |  1 +
 erlang/apps/sim/test/sim_boolean_tests.erl | 12 +++++++++++
 3 files changed, 36 insertions(+)

diff --git a/erlang/apps/sim/src/sim_boolean.erl b/erlang/apps/sim/src/sim_boolean.erl
index 457a519..8801d6b 100644
--- a/erlang/apps/sim/src/sim_boolean.erl
+++ b/erlang/apps/sim/src/sim_boolean.erl
@@ -26,6 +26,7 @@
 
 -export([ handle_AND/4
         , handle_ANDI/4
+        , handle_ANDM/4
         , handle_SETZ/4
         , handle_SETZB/4
         , handle_SETZM/4
@@ -89,6 +90,28 @@ handle_ANDI(Core, Mem, IR, EA) ->
   Word = CA band EA#ea.offset,
   sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem).
 
+-spec handle_ANDM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
+      -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
+handle_ANDM(Core, Mem, IR, EA) ->
+  case sim_core:c(Core, Mem, EA) of
+    {ok, CE} ->
+      AC = IR band 8#17,
+      CA = sim_core:get_ac(Core, AC),
+      Word = CE band CA,
+      handle_ANDM_1(Core, Mem, EA, Word);
+    {error, Reason} ->
+      sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
+                          fun(Core1, Mem1) -> handle_ANDM(Core1, Mem1, IR, EA) end)
+  end.
+
+handle_ANDM_1(Core, Mem, EA, Word) ->
+  case sim_core:cset(Core, Mem, EA, Word) of
+    {ok, Core1} -> sim_core:next_pc(Core1, Mem);
+    {error, Reason} ->
+      sim_core:page_fault(Core, Mem, ea_address(EA), write, Reason,
+                          fun(Core1, Mem1) -> handle_ANDM_1(Core1, Mem1, EA, Word) end)
+  end.
+
 %% Miscellaneous ===============================================================
 
 ea_address(#ea{section = Section, offset = Offset}) ->
diff --git a/erlang/apps/sim/src/sim_core.erl b/erlang/apps/sim/src/sim_core.erl
index e8df74e..59482ea 100644
--- a/erlang/apps/sim/src/sim_core.erl
+++ b/erlang/apps/sim/src/sim_core.erl
@@ -259,6 +259,7 @@ dispatch(Core, Mem, IR, EA) ->
     8#403 -> sim_boolean:handle_SETZB(Core, Mem, IR, EA);
     8#404 -> sim_boolean:handle_AND(Core, Mem, IR, EA);
     8#405 -> sim_boolean:handle_ANDI(Core, Mem, IR, EA);
+    8#406 -> sim_boolean:handle_ANDM(Core, Mem, IR, EA);
     _ ->
       PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
       {Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}
diff --git a/erlang/apps/sim/test/sim_boolean_tests.erl b/erlang/apps/sim/test/sim_boolean_tests.erl
index c18d81e..f504f92 100644
--- a/erlang/apps/sim/test/sim_boolean_tests.erl
+++ b/erlang/apps/sim/test/sim_boolean_tests.erl
@@ -49,6 +49,7 @@
 -define(OP_SETZB, 8#403).
 -define(OP_AND, 8#404).
 -define(OP_ANDI, 8#405).
+-define(OP_ANDM, 8#406).
 
 %% 2.4 Boolean Functions =======================================================
 
@@ -119,6 +120,17 @@ andi_test() ->
          [ {#ea{section = 1, offset = 1, islocal = false}, 8#303030} % AC1 = 0,,303030
          ]).
 
+andm_test() ->
+  Prog =
+    [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 8#707070)} % 1,,100/ MOVEI 1,707070
+    , {1, 8#101, ?INSN(?OP_ANDM, 1, 0, 0, 8#200)}     % 1,,101/ ANDM 1,200
+    , {1, 8#102, ?INSN_INVALID}                       % 1,,102/ <invalid>
+    , {1, 8#200, ?COMMA2(-1, 8#333333)}               % 1,,200/ -1,333333
+    ],
+  expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
+         [ {#ea{section = 1, offset = 8#200, islocal = false}, 8#303030} % C(1,,200) = 0,,303030
+         ]).
+
 %% Common code to run short sequences ==========================================
 
 expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->