diff --git a/erlang/apps/sim/src/sim_core.erl b/erlang/apps/sim/src/sim_core.erl index c0648dd..7eb9e12 100644 --- a/erlang/apps/sim/src/sim_core.erl +++ b/erlang/apps/sim/src/sim_core.erl @@ -329,6 +329,10 @@ dispatch(Core, Mem, IR, EA) -> 8#521 -> sim_halfword:handle_HLLOI(Core, Mem, IR, EA); 8#522 -> sim_halfword:handle_HLLOM(Core, Mem, IR, EA); 8#523 -> sim_halfword:handle_HLLOS(Core, Mem, IR, EA); + 8#530 -> sim_halfword:handle_HLLE(Core, Mem, IR, EA); + 8#531 -> sim_boolean:handle_SETZ(Core, Mem, IR, EA); % HLLEI = HLLZI = SETZ + 8#532 -> sim_halfword:handle_HLLEM(Core, Mem, IR, EA); + 8#533 -> sim_halfword:handle_HLLES(Core, Mem, IR, EA); _ -> PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset, {Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}} diff --git a/erlang/apps/sim/src/sim_halfword.erl b/erlang/apps/sim/src/sim_halfword.erl index 549ff18..db747e4 100644 --- a/erlang/apps/sim/src/sim_halfword.erl +++ b/erlang/apps/sim/src/sim_halfword.erl @@ -25,6 +25,9 @@ -module(sim_halfword). -export([ handle_HLL/4 + , handle_HLLE/4 + , handle_HLLEM/4 + , handle_HLLES/4 , handle_HLLI/4 , handle_HLLM/4 , handle_HLLS/4 @@ -181,6 +184,42 @@ handle_HLLOS(Core, Mem, IR, EA) -> fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) end. +%% HLLE - Half Word Left to Left, Extend + +-spec handle_HLLE(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLLE(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = set_left_extend(get_left(CE)), + sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + +-spec handle_HLLEM(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLLEM(Core, Mem, IR, EA) -> + AC = IR band 8#17, + CA = sim_core:get_ac(Core, AC), + Word = set_left_extend(get_left(CA)), + handle_writeback(Core, Mem, EA, Word). + +-spec handle_HLLES(#core{}, sim_mem:mem(), IR :: word(), #ea{}) + -> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}. +handle_HLLES(Core, Mem, IR, EA) -> + case sim_core:c(Core, Mem, EA) of + {ok, CE} -> + AC = IR band 8#17, + Word = set_left_extend(get_left(CE)), + handle_writeback(Core, Mem, AC, EA, Word); + {error, Reason} -> + sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason, + fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end) + end. + %% Miscellaneous =============================================================== handle_writeback(Core, Mem, EA, Word) -> @@ -211,6 +250,10 @@ get_right(Word) -> Word band ((1 bsl 18) - 1). set_left(Word, Left) -> get_right(Word) bor (Left bsl 18). +set_left_extend(Left) -> + Right = (0 - ((Left bsr 17) band 1)) band ((1 bsl 18) - 1), + (Left bsl 18) bor Right. + set_left_ones(Left) -> (Left bsl 18) bor ((1 bsl 18) - 1). set_left_zeros(Left) -> Left bsl 18. diff --git a/erlang/apps/sim/test/sim_halfword_tests.erl b/erlang/apps/sim/test/sim_halfword_tests.erl index cc4c8df..567d275 100644 --- a/erlang/apps/sim/test/sim_halfword_tests.erl +++ b/erlang/apps/sim/test/sim_halfword_tests.erl @@ -57,6 +57,10 @@ -define(OP_HLLOI, 8#521). -define(OP_HLLOM, 8#522). -define(OP_HLLOS, 8#523). +-define(OP_HLLE, 8#530). +-define(OP_HLLEI, 8#531). +-define(OP_HLLEM, 8#532). +-define(OP_HLLES, 8#533). %% 2.8 Half-Word Data Transmission ============================================= @@ -257,6 +261,64 @@ hllos_no_ac_test() -> , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(0, 1)} % AC0 = 0,,1 ]). +%% HLLE - Half Word Left to Left, Extend + +hlle_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HLLE, 1, 0, 0, 8#200)} % 1,,101/ HLLE 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(-1, 0)} % 1,,200/ -1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, -1)} % AC1 = -1,,-1 + ]). + +hllei_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 0,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HLLEI, 1, 0, 0, 0)} % 0,,101/ HLLEI 1,0 + , {1, 8#102, ?INSN_INVALID} % 0,,102/ + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 1, islocal = false}, 0} % AC1 = 0 + ]). + +hllem_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1 + , {1, 8#101, ?INSN(?OP_HLLEM, 1, 0, 0, 8#200)} % 1,,101/ HLLEM 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(0, 1)} % 1,,200/ 0,,1 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(1, 0)} % C(1,,200) = 1,,0 + ]). + +hlles_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1 + , {1, 8#101, ?INSN(?OP_HLLES, 1, 0, 0, 8#200)} % 1,,101/ HLLES 1,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(-1, 0)} % 1,,200/ -1,,0 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(-1, -1)} % C(1,,200) = -1,,-1 + , {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, -1)} % AC1 = -1,,-1 + ]). + +hlles_no_ac_test() -> + Prog = + [ {1, 8#100, ?INSN(?OP_MOVEI, 0, 0, 0, 1)} % 1,,100/ MOVEI 0,1 + , {1, 8#101, ?INSN(?OP_HLLES, 0, 0, 0, 8#200)} % 1,,101/ HLLES 0,200 + , {1, 8#102, ?INSN_INVALID} % 1,,102/ + , {1, 8#200, ?COMMA2(1, 1)} % 1,,200/ 1,,1 + ], + expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS, + [ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(1, 0)} % C(1,,200) = 1,,0 + , {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(0, 1)} % AC0 = 0,,1 + ]). + %% Common code to run short sequences ========================================== expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->