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80 lines
3.6 KiB
Plaintext
80 lines
3.6 KiB
Plaintext
doc/Interrupts.txt
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Copyright (C) 2015-2017 Mikael Pettersson
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This file is part of pdp10-tools.
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pdp10-tools is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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pdp10-tools is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with pdp10-tools. If not, see <http://www.gnu.org/licenses/>.
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PDP10 Interrupt Architecture
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============================
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The PDP10 interrupt architecture is based on two cooperating systems:
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- the Priority Interrupt system, which determines which interrupts are enabled,
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and allows software to enable or disable specific interrupt levels; and
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- the Interrupt Dispatch system, which determines how the processor handles an
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interrupt once it has been accepted.
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The Priority Interrupt System
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-----------------------------
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The PDP10 has 8 interrupt levels, numbered 0-7, with 0 having highest priority.
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Levels 1-7 can be individually masked or unmasked, level 0 cannot be masked.
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Devices can be assigned any level from 1 to 7 (assigning level 0 disconnects it).
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Devices can share levels.
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A device sends an interrupt request by signalling its assigned level to the processor.
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The request is recognized if both the priority interrupt system and the specific level
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are enabled, and the processor is not already handling a request at the same or higher
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priority.
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Once the processor starts handling an interrupt, it is held until dismissed.
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While held, all interrupts at that and lower priority leves are blocked.
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WRPI aka "CONO 4, EA" writes to the priority interrupt system.
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RDPI aka "CONI 4, EA" reads the current interrupt mask.
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The Interrupt Dispatch System
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-----------------------------
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Early processors (PDP6, KA10, KI10, KL10, KS10) handle a recognized interrupt by
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executing an "interrupt instruction" at a level-specific location. An interrupt
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instruction is encoded as an ordinary PDP10 instruction, but only a subset of PDP10
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instructions are permitted, and the state (PC and registers) is still that of the
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interrupted context. In practice, this limits the permissible instructions to
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simple I/O transfers or calls to service routines.
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On the extended KL10, the preferred interrupt instruction for calling a service
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routine is XPCW, and the service routine should then return with XJEN (JRST 7,).
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On non-extended processors, the instructions to use are JSR and JEN (JRST 12,).
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Later processors (KC10, XKL-1) eliminate interrupt instructions and instead require
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vectors of "interrupt control blocks" for use by implicit XPCW instructions.
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The different processor generations vary in:
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1. Which instructions, if any, are permitted as interrupt instructions.
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2. The exact locations of the dispatch vectors. Locations 040-057 are commonly used in
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early processors, while later processors use different locations in the EPT.
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3. The exact hardware protocol by which the interrupting device informs the processor
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about how to handle the interrupt (KL10 has additional features here).
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References
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----------
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- TOAD-1 System Architecture Reference Manual, Chapter 4 "Earlier Processors",
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Section 4.1 "KL10 System Operations", Subsection 4.1.1 "Priority Interrupt", pages 334-342.
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- TOAD-1 System Architecture Reference Manual, Chapter 3 "TOAD-1 System and
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XKL-1 Processor Operations", Section 3.1 "Priority Interrupt", pages 212-221.
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- KC10 Exec Mode, Rev. 6
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