mirror of
https://github.com/mikpe/pdp10-tools.git
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214 lines
8.1 KiB
Erlang
214 lines
8.1 KiB
Erlang
%%% -*- erlang-indent-level: 2 -*-
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%%%
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%%% pdp10_opcodes.hrl
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%%% Copyright (C) 2013-2019 Mikael Pettersson
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%%%
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%%% This file is part of pdp10-tools.
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%%%
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%%% pdp10-tools is free software: you can redistribute it and/or modify
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%%% it under the terms of the GNU General Public License as published by
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%%% the Free Software Foundation, either version 3 of the License, or
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%%% (at your option) any later version.
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%%%
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%%% pdp10-tools is distributed in the hope that it will be useful,
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%%% but WITHOUT ANY WARRANTY; without even the implied warranty of
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%%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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%%% GNU General Public License for more details.
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%%%
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%%% You should have received a copy of the GNU General Public License
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%%% along with pdp10-tools. If not, see <http://www.gnu.org/licenses/>.
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-ifndef(PDP10_OPCODES_HRL).
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-define(PDP10_OPCODES_HRL, 1).
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%% Data Representation
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%% ===================
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%%
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%%
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%% 11111111112222222222333333
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%% 012345678901234567890123456789012345
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%% +------------------------------------+
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%% | |
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%% +------------------------------------+
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%%
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%% The basic storage unit is a 36-bit wide word. Its bits are numbered 0
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%% to 35, in left-to-right order, with bit 0 being the most significant
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%% and bit 35 the least significant.
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%%
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%% The architecture supports sub-word storage units via special instructions
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%% and specially formatted "byte" pointers, where a byte may be from 0 to 36
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%% bits wide. Incrementing a byte pointer moves it right over the word towards
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%% its less significant bits, indicating a big-endian byte order.
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%%
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%% A 72-bit long integer consists of two adjacent words, with the most
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%% significant bits in the first word (lower address) and the least significant
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%% bits in the second word (higher address), indicating a big-endian word order.
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%% Instruction Representation
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%% ==========================
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%%
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%% Basic instructions are stored in 36-bit words with the following format:
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%%
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%% 111 1 1111 112222222222333333
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%% 012345678 9012 3 4567 890123456789012345
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%% +---------+----+-+----+------------------+
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%% | opcode | A |I| X | Y |
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%% +---------+----+-+----+------------------+
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%% 9 bits 4 1 4 18 bits
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%%
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%% A 9-bit opcode is stored in the high 9 bits.
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%% A is a 4-bit field specifying the accumulator (a register).
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%% I is a 1-bit field specifying indirect addressing.
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%% X is a 4-bit field specifying the index register.
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%% Y is an 18-bit field specifying an address or offset.
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%%
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%% E, the effective addreess, is computed from I, X, and Y.
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%%
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%% In some instructions A contains further opcode bits.
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%%
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%% In some instructions A is unused and should be zero.
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%%
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%% In some instructions A must be non-zero.
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%%
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%% Instructions that not compute an effective address E
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%% should have I, X, and Y set to zero.
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%%
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%% IO instructions have a slightly different format:
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%%
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%% 111 1 1111 112222222222333333
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%% 012 3456789 012 3 4567 890123456789012345
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%% +---+-------+---+-+----+------------------+
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%% |op1| device|op2|I| X | Y |
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%% +---+-------+---+-+----+------------------+
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%% 3 7 bits 3 1 4 18 bits
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%%
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%% The op1 field is all-bits-one (7), the device field addresses the selected
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%% device, and the op2 field specifies the operation. Both devices internal to
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%% the processor and devices attached via external buses can be accessed.
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%%
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%% Some non-IO instructions also have a 7 in their high three bits.
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%%
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%% Extended instructions consist of two separate instruction words:
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%%
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%% A:
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%% 111 1 1111 112222222222333333
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%% 012345678 9012 3 4567 890123456789012345
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%% +---------+----+-+----+------------------+
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%% | 0123 | A |I| X | Y |
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%% +---------+----+-+----+------------------+
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%% 9 bits 4 1 4 18 bits
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%%
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%% E0:
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%% 111 1 1111 112222222222333333
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%% 012345678 9012 3 4567 890123456789012345
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%% +---------+----+-+----+------------------+
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%% | xopcode |0000|I| X | Y |
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%% +---------+----+-+----+------------------+
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%% 9 bits 4 1 4 18 bits
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%%
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%% The first word is stored at address A in the instruction stream, in the basic
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%% format with opcode 0123. The second word is stored at the effective address
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%% E0 specified by the the first word. Its accumulator field is unused and must
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%% be zero for compatibility with future extensions.
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%% Known PDP10 CPU models, each represented by a distinct bit value.
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%%
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%% These are combined with bit-wise 'and', 'or', and 'not' operations
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%% to form sets of CPU models, used to check if a given mnemonic or
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%% opcode is available for a selected set of CPUs.
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%% DEC processors.
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-define(PDP6, (1 bsl 0)). % PDP-6 Type 166 Arithmetic Processor
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-define(PDP10_KA10, (1 bsl 1)). % KA10
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-define(PDP10_KA10_ITS, (1 bsl 2)). % KA10, ITS microcode
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-define(PDP10_KI10, (1 bsl 3)). % KI10
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-define(PDP10_KL10, (1 bsl 4)). % KL10 (early, non-extended)
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-define(PDP10_KL10_ITS, (1 bsl 5)). % KL10, ITS microcode
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-define(PDP10_KL10_271, (1 bsl 6)). % KL10B, microcode >= 271, extended
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-define(PDP10_KS10, (1 bsl 7)). % KS10
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-define(PDP10_KS10_ITS, (1 bsl 8)). % KS10, ITS microcode
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%% XKL Processors.
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-define(PDP10_XKL1, (1 bsl 9)). % XKL-1 / TOAD-1
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-define(PDP10_LAST, ?PDP10_XKL1).
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%% Others, not yet supported:
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%%
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%% DEC KC10 (Jupiter, KL10B successor with full extended addressing, not built)
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%% DEC KD10 (Minnow, KS10 successor with full extended addressing, not built)
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%%
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%% XKL-2 (XKL-1 successor, no documentation available)
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%%
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%% System Concepts SC-20, SC-25, SC-30M, SC-40 (KC10-like)
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%%
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%% Foonly F-1, F-2, F-3, F-4 (KI10/KL10-hybrid)
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%%
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%% Xerox PARC MAXC (KI10-like?)
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%% Convenience constants for combinations of CPU models.
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-define(PDP10_ALL, (?PDP10_LAST bor (?PDP10_LAST - 1))).
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-define(PDP10_KL10_271up, (?PDP10_KL10_271 bor ?PDP10_XKL1)).
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-define(PDP10_KL10any, (?PDP10_KL10 bor ?PDP10_KL10_ITS bor ?PDP10_KL10_271up)).
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-define(PDP10_KL10up, (?PDP10_KL10any bor ?PDP10_KS10)).
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-define(PDP10_KI10_to_KL10, (?PDP10_KI10 bor ?PDP10_KL10any)).
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-define(PDP10_KI10up, (?PDP10_KI10 bor ?PDP10_KL10up)).
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-define(PDP10_ITS, (?PDP10_KA10_ITS bor ?PDP10_KL10_ITS bor ?PDP10_KS10_ITS)).
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-define(PDP10_KA10any, (?PDP10_KA10 bor ?PDP10_KA10_ITS)).
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-define(PDP10_KA10up, (?PDP10_KA10any bor ?PDP10_KI10up)).
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-define(PDP10_KA10up_not_ITS, (?PDP10_KA10up band bnot ?PDP10_ITS)).
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-define(PDP10_KA10_to_KI10, (?PDP10_KA10 bor ?PDP10_KI10)). % FIXME: should that be KA10any?
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-define(PDP10_KA10_to_KL10, (?PDP10_KA10_to_KI10 bor ?PDP10_KL10any)).
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-define(PDP10_not_KS10_or_XKL1, (?PDP10_ALL band bnot (?PDP10_KS10 bor ?PDP10_XKL1))). % FIXME: should that be KS10any?
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-define(PDP6_to_KI10, (?PDP6 bor ?PDP10_KA10_to_KI10)).
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-type pdp10_cpu_models() :: 0..?PDP10_ALL.
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%% Device fields in IO instructions.
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-type pdp10_cpu_device() :: 0..127.
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%% Each instruction belongs to exactly one of these primary categories,
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%% which determine how the high 13 bits are to be interpreted.
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-define(PDP10_INSN_BASIC, 'PDP10_INSN_BASIC').
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-define(PDP10_INSN_A_OPCODE, 'PDP10_INSN_A_OPCODE').
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-define(PDP10_INSN_A_NONZERO, 'PDP10_INSN_A_NONZERO').
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-define(PDP10_INSN_IO, 'PDP10_INSN_IO').
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-type pdp10_insn_format() :: ?PDP10_INSN_BASIC
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| ?PDP10_INSN_A_OPCODE
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| ?PDP10_INSN_A_NONZERO
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| ?PDP10_INSN_IO.
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%% Instruction descriptors.
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-record(pdp10_insn_desc,
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{ name :: string()
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%% The high13 field is 13 bits, formatted as:
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%% <9 bit opcode><0000> BASIC, A_NONZERO
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%% <9 + 4 bit opcode> A_OPCODE
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%% <111><0000000><3 bit op> IO
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%%
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%% An extended instruction uses the BASIC format with opcode 0123 for
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%% the first word, and the A_OPCODE(00) EXTENDED format for the second word.
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, high13 :: 0..((1 bsl 13) - 1)
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, format :: pdp10_insn_format()
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, e_unused = false :: boolean()
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, extended = false :: boolean()
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, models :: pdp10_cpu_models()
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, section0 = undefined :: undefined | true | false
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, priority = undefined :: undefined | non_neg_integer()
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}).
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-endif. % PDP10_STDINT_HRL
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