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114 lines
4.1 KiB
C
114 lines
4.1 KiB
C
/*
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* pdp10-core.h -- core definitions for PDP10 simulation
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* Copyright (C) 2018 Mikael Pettersson
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*
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* This file is part of pdp10-tools.
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*
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* pdp10-tools is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* pdp10-tools is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with pdp10-tools. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PDP10_CORE_H
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#define PDP10_CORE_H
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#include <assert.h>
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#include "pdp10-stdint.h"
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#include "pdp10-virt-mem.h"
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/*
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* Words are 36 bits wide. The bits are numbered 0-35, left to right (most
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* significant to least significant). The left (more significant) half word
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* is bits 0-17, and the right (less significant) half word is bits 18-36.
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* Numbers use twos-complement representation, with bit 0 as the sign.
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*
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* A double word is two adjacent words treated as a single 72-bit entity, where
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* the word with the lower address is the more significant.
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*
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* Bits are numbered in decimal, most other numbers are in octal, in particular
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* accumulator numbers, addresses, and instruction codes are in octal.
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*
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* A virtual address on a fully extended processor is 30 bits, composed of a 12
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* bit section number (upper 12 bits) and an 18-bit section offset (lower 18
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* bits). Paging hardware divides each section into 512 pages of 512 words each.
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* The address bits are numbered according to the right-justified position of an
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* address in a word. Thus bits 6-17 contain the section number, and bits 18-35
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* the section offset.
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*
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* Single-section processors (PDP6, KA10, KI10, non-extended KL10, KS10) have no
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* section number in their virtual addresses, while the extended KL10 (KL10B)
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* only has 5 bit section numbers (bits 13-17).
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*
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* The program counter register, PC, contains a virtual address. Incrementing PC
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* increments its segment offset without propagating any carry into the section
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* number.
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*
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* Instructions are words. In the basic instruction format, bits 0-8 specify the
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* operation, and bits 9-12 (A) address an accumulator. The rest of the word
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* specifies how to calculate the effective address (E). Bit 13 (I) specifies the
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* type of addressing (indirect or not), bits 14-17 (X) specify an index register,
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* and bits 18-35 (Y) specify a memory location. Some instructions use bits 9-12
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* to address flags or as extension of the instruction code.
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*
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* If an instruction does not use some part of the instruction word, that part is
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* reserved and MUST BE ZERO, unless otherwise specified.
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*/
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/*
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* BITS36(X, LEFT, RIGHT)
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*
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* Extract bits LEFT through RIGHT (inclusive) from a 36-bit number X.
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* Requires 0 <= LEFT <= RIGHT <= 35.
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*/
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static inline pdp10_uint36_t BITS36(pdp10_uint36_t X, unsigned int LEFT, unsigned int RIGHT)
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{
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assert(0 <= LEFT && LEFT <= RIGHT && RIGHT <= 35);
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return (X >> (35 - RIGHT)) & ((1UL << (1 + RIGHT - LEFT)) - 1);
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}
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static inline uint32_t BITS36LOW18(pdp10_uint36_t X)
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{
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return BITS36(X, 18, 35);
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}
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/*
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* BIT36(X, BIT)
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*
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* Extract bit BIT from a 36-bit number X.
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* Requires 0 <= BIT <= 35.
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*/
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static inline unsigned int BIT36(pdp10_uint36_t X, unsigned int BIT)
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{
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return BITS36(X, BIT, BIT);
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}
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typedef uint32_t pdp10_vaddr_t; /* 30 bits: 12-bit section number, 18-bit section offset */
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struct pdp10_cpu {
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pdp10_vaddr_t PC;
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pdp10_uint36_t AC[017]; /* copy of ACS[CAB] */
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pdp10_uint36_t ACS[8][017];
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unsigned int flags:13;
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unsigned int CAB:3; /* Current AC Block */
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/*
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* Previous Context
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*/
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unsigned int PCS:12; /* Previous Context Section */
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unsigned int PCU:1; /* Previous Context User */
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unsigned int PAB:3; /* Previous AC Block */
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/*
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* Memory
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*/
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struct pdp10_vmem vmem;
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};
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#endif /* PDP10_CORE_H */
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